COM20020I-DZD-TR Standard Microsystems (SMSC), COM20020I-DZD-TR Datasheet - Page 34

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COM20020I-DZD-TR

Manufacturer Part Number
COM20020I-DZD-TR
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of COM20020I-DZD-TR

Number Of Transceivers
1
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
COM20020I-DZD-TR
Manufacturer:
Microchip
Quantity:
1 048
Part Number:
COM20020I-DZD-TR
Manufacturer:
Microchip Technology
Quantity:
10 000
Revision 12-05-06
2,1,0
BIT
BIT
5-3
2-0
7-0
BIT
7-3
7
6
Read Data
Auto Increment
(Reserved)
Address 10-8
Address 7-0
Reserved
Sub Address 2,1,0
BIT NAME
BIT NAME
BIT NAME
RDDATA
AUTOINC
A10-A8
A7-A0
SUBAD
2,1,0
SYMBOL
SYMBOL
SYMBOL
Table 6.6 - Address Pointer High Register
Table 6.7 - Address Pointer Low Register
Table 6.8 - Sub Address Register
DATASHEET
These bits are undefined.
These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD2
SUBAD1 and SUBAD0 are exactly the same as exist in the
Configuration Register. SUBAD2 is cleared automatically by writing
the Configuration Register.
This bit tells the COM20020ID whether the following access will
be a read or write. A logic "1" prepares the device for a read, a
logic "0" prepares it for a write.
This bit controls whether the address pointer will increment
automatically. A logic "1" on this bit allows automatic increment of
the pointer after each access, while a logic "0" disables this
function. Please refer to the Sequential Access Memory section
for further detail.
These bits are undefined.
These bits hold the upper three address bits which provide
addresses to RAM.
These bits hold the lower 8 address bits which provide the
addresses to RAM.
0
0
0
0
1
1
1
1
Page 34
SUBAD1
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
0
0
1
1
0
0
1
1
DESCRIPTION
DESCRIPTION
DESCRIPTION
SUBAD0
1
0
1
0
1
0
1
0
Tentative ID \ (Same
Node ID
Setup 1
Next ID
Setup 2
Reserved
Reserved
Reserved
Register
SMSC COM20020I Rev D
\ as in
/ Config
/ Register)
Datasheet

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