COM20020I-HD Standard Microsystems (SMSC), COM20020I-HD Datasheet
COM20020I-HD
Specifications of COM20020I-HD
Related parts for COM20020I-HD
COM20020I-HD Summary of contents
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... Sequential Access to Internal RAM Software Programmable Node ID COM20020ILJP for 28 pin PLCC package COM20020I-DZD for 28 pin PLCC lead-free RoHS compliant package COM20020I-HD for 48 pin TQFP package COM20020I-HT for 48 pin TQFP lead-free RoHS compliant package SMSC COM20020I Rev D COM20020I Rev D 5Mbps ARCNET (ANSI 878 ...
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... OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 2 DATASHEET Datasheet SMSC COM20020I Rev D ...
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... Selecting RAM Page Size ...................................................................................................................41 6.4.2 Transmit Sequence .............................................................................................................................42 6.4.3 Receive Sequence ..............................................................................................................................44 6.5 Command Chaining....................................................................................................................................45 6.5.1 Transmit Command Chaining .............................................................................................................45 6.5.2 Receive Command Chaining ..............................................................................................................46 6.6 Reset Details..............................................................................................................................................47 6.6.1 Internal Reset Logic ............................................................................................................................47 6.7 Initialization Sequence ...............................................................................................................................47 6.7.1 Bus Determination...............................................................................................................................47 SMSC COM20020I Rev D Page 3 DATASHEET Revision 12-05-06 ...
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... Example of Interface Circuit Diagram to ISA Bus ............................................................. 71 Appendix C - Software Identification of the COM20020 Rev B, Rev C and Rev D ................................ 72 List of Figures Figure 2.1 - Pin Configuration - COM20020I 28-Pin PLCC ............................................................................................7 Figure 2.2 - Pin Configuration - COM20020I 48-Pin TQFP ............................................................................................8 Figure 3.1 - COM20020ID Operation ...........................................................................................................................11 Figure 5.1 – Multiplexed, 8051-Like Bus Interface with RS-485 Interface....................................................................18 Figure 5.2 – ...
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... For more detailed information on cabling options including RS485, transformer-coupled RS-485 and Fiber Optic interfaces, please refer to the following technical note which is available from Standard Microsystems Corporation: Technical Note 7-5 - Cabling Guidelines for the COM20020 ULANC. SMSC COM20020I Rev D Page 5 DATASHEET Revision 12-05-06 ...
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... Chapter 1 General Description SMSC's COM20020ID is a member of the family of Embedded ARCNET Controllers from Standard Microsystems Corporation. The device is a general purpose communications controller for networking microcontrollers and intelligent peripherals in industrial, automotive, and embedded control environments ® using an ARCNET protocol engine. The small 28 pin package, flexible microcontroller and media interfaces, eight- page message support, and extended temperature range of the COM20020ID make it the only true network controller optimized for use in industrial, embedded, and automotive applications ...
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... Pin Configurations nWR/DIR 26 nRD/nDS 27 28 VDD A0/nMUX A2/ALE 3 AD0 Ordering Information: COM20020 I LJP PACKAGE TYPE: "LJP" = Standard (Sn/Pb) plated PLCC TEMP RANGE: DEVICE TYPE: Figure 2.1 - Pin Configuration - COM20020I 28-Pin PLCC SMSC COM20020I Rev Package: 28-Pin PLCC "-DZD" = Pb-free plated PLCC (Blank) = Commercial = 0° ...
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... AD0 1 AD1 2 N/C 3 AD2 4 N/C 5 VSS VDD VSS Figure 2.2 - Pin Configuration - COM20020I 48-Pin TQFP Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM COM20020I 48 PIN TQFP Page 8 DATASHEET Datasheet 36 nCS 35 VDD 34 nINTR 33 N/C 32 VDD 31 nRESET 30 VSS 29 nTXEN 28 RXIN 27 N/C ...
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... In this case, data is actually strobed by the nDS signal 80XX-like bus, nWR is an active low signal issued by the microcontroller to indicate a write operation. In this case, a logic "0" on this pin, when the COM20020ID is accessed, enables data from the data bus to be written to the device. ...
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... An external crystal should be connected to these pins. Oscillation frequency range is from MHz XTAL2 external TTL clock is used instead, it must be connected to XTAL1 with a 390Ω pull-up resistor, and XTAL2 should be left floating Volt Power Supply pin Ground pin. SS Page 10 DATASHEET Datasheet DESCRIPTION SMSC COM20020I Rev D ...
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... N us ACK Set TA NAK? Write Buffer 1 with Packet Pass the Token No Increment Y N Activity NID for 37.4 us? SEND ACK Figure 3.1 - COM20020ID Operation Page 11 DATASHEET 1 N SOH Activity for 41 uS? Y DID Y =0? Set NID= Broadcast Enabled? DID Start Timer: =ID? T=(255-ID) ...
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... Data Rates The COM20020ID is capable of supporting data rates from 156.25 Kbps to 5 Mbps. The following protocol description assumes a 5 Mbps data rate. To attain the faster data rates, the clock frequency may be doubled by the internal clock multiplier (see next section). For slower data rates, an internal clock divider scales down the clock frequency ...
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... COM20020ID releases control of the line. INVITATIONS TO TRANSMIT are sent to all NIDs (1-255). Each COM20020ID on the network will finally have saved a NID value equal to the ID of the COM20020ID that it released control to. At this point, control is passed directly from one node to the next with no wasted INVITATIONS TO TRANSMIT being sent to ID's not on the network, until the next NETWORK RECONFIGURATION occurs ...
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... All other nodes on the network must distinguish between this operation and an entirely idle line. During NETWORK RECONFIGURATION, activity will appear on the line every 41 μS. This 41 μS is equal to the Response Time of 37.4 μS plus the time it takes the COM20020ID to start retransmitting another message (usually another INVITATION TO TRANSMIT). ...
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... COUNT character if a long packet is sent. N data bytes where COUNT = 256-N (or 512-N for a long packet) Two CRC (Cyclic Redundancy Check) characters. The CRC polynomial used is: X ALERT SOH SID BURST SMSC COM20020I Rev D ALERT EOT DID BURST ALERT ENQ ...
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... A Negative Acknowledgement is used as a negative response to FREE BUFFER ENQUIRIES and is sent by the following sequence: An ALERT BURST A NAK (Negative Acknowledgement--ASCII code 15H) character Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM ALERT BURST ACK ALERT BURST NAK Page 16 DATASHEET Datasheet SMSC COM20020I Rev D ...
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... Since microcontrollers do not typically have READY inputs, standard peripherals cannot extend cycles to extend the access time. The access time of the COM20020ID, on the other hand fast that it does not need to limit the speed of the microcontroller. The COM20020ID is designed to be flexible so that it is independent of the microcontroller speed ...
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... GND nINTR XTAL1 XTAL2 A0/nMU MHz XTAL +5V RXIN 100 nPULSE NOTE: COM20020 must be in backplane mode Page 18 DATASHEET Datasheet 75176B or Equiv. Differential Configuratio Media * may be with Figure +5V 2 Receive 6 HFD3212- 7 Transmitte HFE4211 Fiber (ST FIGURE B SMSC COM20020I Rev D ...
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... XTAL1 XTAL2 D0- nRES nIOS R/nW nIRQ1 6801 RXIN nTXEN nPULSE1 nPULSE2 GND Figure 5.2 – Non-Multiplexed, 6801-Like Bus Interface with RS-485 Interface SMSC COM20020I Rev D COM20020ID D0-D7 A0/nMUX RXIN A1 A2/BALE TXEN nCS nPULSE1 nRESET nPULSE2 nRD/nDS GND nWR/nDIR nINTR XTAL1 XTAL2 ...
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... High Speed CPU Bus Timing Support High speed CPU bus support was added to the COM20020ID. The reasoning behind this is as follows: With the Host interface in Non-multiplexed Bus mode, I/O address and Chip Select signals must be stable before the read signal is active and remain after the read signal is inactive. But the High Speed CPU bus timing doesn't adhere to these timings ...
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... A logic "0" is transmitted by the absence of the dipulse. During reception, the 200nS dipulse appearing on the media is coupled through the RF transformer of the LAN Driver, which produces a positive pulse at the RXIN pin of the COM20020ID. The pulse on the RXIN pin represents a logic "1". Lack of pulse represents a logic "0". ...
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... It issues a 200nS negative pulse to transmit a logic "1". Note that when used in the open-drain mode, the COM20020ID does not have a fail/safe input on the RXIN pin. The nPULSE1 signal actually contains a weak pull-up resistor. This pull-up should not take the place of the resistor required on the media for open drain mode ...
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... COM20020ID. The nPULSE1 signal transmits the data, provided the Transmit Enable signal is active. The nPULSE1 signal issues a 200nS (at 2.5Mbps) negative pulse to transmit a logic "1". Lack of pulse indicates a logic "0". The RXIN signal receives the data, the transmitter portion of the COM20020ID is disabled during reset and the nPULSE1, nPULSE2 and nTXEN pins are inactive. ...
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... Table 5.1 - Typical Media NOMINAL IMPEDANCE 93Ω 75Ω 75Ω 150Ω 100Ω 105Ω Page 24 DATASHEET Datasheet ADDITIONAL REGISTERS nPULSE1 nPULSE2 TX/RX nTXEN LOGIC RXIN XTAL1 OSCILLATOR XTAL2 LOGIC ATTENUATION PER 1000 FT MHZ 5.5dB 7.0dB 5.5dB 7.0dB 17.9dB 16.0dB SMSC COM20020I Rev D ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet Note: For more detailed information on Cabling options including RS-485, transformer-coupled RS-485 and Fiber Optic interfaces, please refer to TN7-5 – Cabling Guidelines for the COM20020 ULANC, available from Standard Microsystems Corporation. SMSC COM20020I Rev D Page 25 DATASHEET Revision 12-05-06 ...
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... The COM20020ID derives a 10 MHz and a 5 MHz clock from the output clock of the Clock Multiplier. These clocks provide the rate at which the instructions are executed within the COM20020ID. The 10 MHz clock is the rate at which the program counter operates, while the 5 MHz clock is the rate at which the instructions are executed ...
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... Interrupt Mask Register (IMR) The COM20020ID is capable of generating an interrupt signal when certain status bits become true. A write to the IMR specifies which status bits will be enabled to generate an interrupt. The bit positions in the IMR are in the same position as their corresponding status bits in the Status Register and Diagnostic Status Register. A logic " ...
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... Node ID. Refer to the Initialization Sequence section for further detail on the use of the DUPID bit. The core of the COM20020ID does not wake up until a Node ID other than zero is written into the Node ID Register. During this time, no microcode is executed, no tokens are passed by this node, and no reconfigurations are caused by this node ...
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... Status Register The COM20020ID Status Register is an 8-bit read-only register. All of the bits, except for bits 5 and 6, are software compatible with previous SMSC ARCNET devices. In previous SMSC ARCNET devices the Extended Timeout status was provided in bits 5 and 6 of the Status Register. In the COM20020ID, the COM20020, the COM90C66, and the COM90C165, COM20020-5, COM20051 and COM20051+ these bits exist in and are controlled by the Configuration Register ...
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... MHz crystal. The RBUSTMG bit is used to Disable/Enable Fast Read function for High Speed CPU bus support. The EF bit is used to enable the new timing for certain functions in the COM20020ID ( the timing is the same as in the COM20020 Rev. B). See Appendix A. The NOSYNC bit is used to enable the NOSYNC function during initialization ...
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... NAK. These bits are undefined. This bit, if high, indicates that the COM20020ID has been reset by either a software reset, a hardware reset, or writing 00H to the Node ID Register. The POR bit is cleared by the "Clear Flags" command. ...
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... Reading the Diagnostic Status Register does not clear this bit. This bit, when set, will cause an interrupt if the corresponding bit in the IMR is also set. The bit is cleared by reading the Next ID Register. These bits are undefined. Page 32 DATASHEET Datasheet SMSC COM20020I Rev D ...
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... If "c" logic "0", the device handles only short packets. This command resets certain status bits of the COM20020ID. A logic "1" on "p" resets the POR status bit and the EXCNAK Diagnostic status bit. A logic "1" on "r" resets the RECON status bit. ...
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... Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM Table 6.6 - Address Pointer High Register This bit tells the COM20020ID whether the following access will be a read or write. A logic "1" prepares the device for a read, a logic "0" prepares it for a write. ...
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... SMSC COM20020I Rev D Table 6.9 - Configuration Register DESCRIPTION A software reset of the COM20020ID is executed by writing a logic "1" to this bit. A software reset does not reset the microcontroller interface mode, nor does it affect the Configuration Register. The only registers that the software reset affect are the Status Register, the Next ID Register, and the Diagnostic Status Register. This bit must be brought back to logic " ...
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... This bit, when set, will cause the EXNACK bit in the Diagnostic Status Register to set after four NACKs to Free Buffer Enquiry are detected by the COM20020ID. This bit, when reset, will set the EXNACK bit after 128 NACKs to Free Buffer Enquiry. The default is 128 ...
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... Write command '18H' (start internal operation) Start initializing routine (Execute existing software) This bit is used to enable the new enhanced functions in the COM20020ID Disable (Default Enable the timing and function is the same as in the COM20020, Revision B. See Appendix A. EF bit must be ‘1’ if the data rate is over 5Mbps. EF bit should be ‘ ...
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... Mbps. RCNTM1 RCNTM0 Time Out Period 0 0 420 105 52 26.25 mS* Note*: The node ID value 255 must exist in the network for 26.25 mS timeout to be valid. Page 38 DATASHEET Datasheet Max Node Count Up to 255 nodes nodes nodes nodes SMSC COM20020I Rev D ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet D0-D7 I/O Address 02H SMSC COM20020I Rev D Data Register I/O Address 04H Memory Data Bus 8 Address Pointer Register I/O Address 03H High Low Memory Address Bus 11-Bit Counter 11 Figure 6.1 - Sequential Access Operation ...
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... Internal RAM The integration of the RAM in the COM20020ID represents significant real estate savings. The most obvious benefit is the 48 pin package in which the device is now placed (a direct result of the integration of RAM). In addition, the PC board is now free of the cumbersome external RAM, external latch, and multiplexed address/data bus and control functions which were necessary to interface to the RAM ...
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... Please note that it is the responsibility of software to reserve 512 bytes for each receive page if the device is configured to handle long packets. The COM20020ID does not check page boundaries during reception. If the device is configured to handle only short packets, then both transmit and receive pages may be allocated as 256 bytes long, freeing at least 1KByte at any given time ...
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... During a transmit sequence, the microcontroller selects a 256 or 512 byte segment of the RAM buffer and writes into it. The appropriate buffer size is specified in the "Define Configuration" command. When long packets are enabled, the COM20020ID interprets the packet as either a long or short packet, depending on whether the buffer address 2 contains a zero or non-zero value. The format of the buffer is shown in Figure 6.2. Address 0 contains the Source Identifier (SID) ...
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... The SID in Address 0 is used by the receiving node to reply to the transmitting node. The COM20020ID puts the local ID in this location, therefore it is not necessary to write into this location. Please note that a short packet may contain between 1 and 253 data bytes, while a long packet may contain between 257 and 508 data bytes ...
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... RAM buffer other than the SID and DID. Once the packet is received and stored correctly in the selected buffer, the COM20020ID sets the RI bit to logic "1" to signal the microcontroller that the reception is complete. ...
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... Transmit from Page fnn" command. The COM20020ID stores the fact that the second transmit command was issued, along with the page number. After the first transmission is completed, the COM20020ID updates the Status Register by setting the TTA bit, which generates an interrupt. The interrupt service routine should read the Status Register. At this point, the TTA bit will be found logic " ...
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... Register will again be updated with the results of the second reception and a second interrupt resulting from the second reception will occur. In the COM20020ID, the Receive Inhibit (RI) bit of the Interrupt Mask Register now masks only the TRI bit of the Status Register, not the RI bit as in the non-chaining mode. Since the TRI bit is only set upon reception of a packet (not by RESET), and since the TRI bit may easily be reset by issuing a " ...
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... Setup1 Register should be written before the Node ID Register. Once the Node ID Register is written to, the COM20020ID reads the value and executes two write cycles to the RAM buffer. Address 0 is written with the data D1H and address 1 is written with the Node ID. The data pattern D1H was chosen arbitrarily, and is meant to provide assurance of proper microsequencer operation ...
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... Tentative ID. To determine the next logical node, the software should read the Next ID Register. 6.8 Improved Diagnostics The COM20020ID allows the user to better manage the operation of the network through the use of the internal Diagnostic Status Register. A high level on the My Reconfiguration (MYRECON) bit indicates that the Token Reception Timer of this node expired, causing a reconfiguration by this node ...
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... Tentative ID Register and monitor the New Next ID bit to maintain an updated network map. 6.9 Oscillator The COM20020ID contains circuitry which, in conjunction with an external parallel resonant crystal or TTL clock, forms an oscillator external crystal is used, two capacitors are needed (one from each leg of the crystal to ground). No external resistor is required, since the COM20020ID contains an internal resistor ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM COM20020I SYMBOL MIN TYP V IL1 V 2.0 IH1 V IL2 V 4.0 IH2 V 1.8 ILH V 1.2 IHL Page 50 DATASHEET Datasheet + +150 DD MAX UNIT COMMENT 0.8 V TTL Levels V TTL Levels 1.0 V TTL Clock Input V V Schmitt Trigger, All Values SMSC COM20020I Rev +0.3V = ...
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... Low Output Voltage 4 (nPULSE1 in Open-Drain Mode) Dynamic V Supply DD Current Input Pull-up Current (nPULSE1 in Open-Drain Mode, A1, AD0-AD2, D3-D7) Input Leakage Current (All inputs except A1, AD0-AD2, D3-D7, XTAL1, XTAL2 SMSC COM20020I Rev D SYMBOL MIN TYP V OL1 V 2.4 OH1 V 0 OH1C DD V OL2 V 2 ...
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... Outputs are measured at 2.0V min. for logic "1" and 0.8V max. for logic "0". Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM = 1MHz 0V MIN TYP MAX C 5 OUT1 400 OUT2 Outputs: t 2.0V 0.8V 2.0V 0.8V t Page 52 DATASHEET Datasheet UNIT COMMENT pF pF Maximum Capacitive Load which can be supported by each output. pF SMSC COM20020I Rev D ...
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... COM20020 cycles. Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 8.1 – Multiplexed Bus, 68XX-Like Control Signals; Read Cycle SMSC COM20020I Rev D VALID VALID DATA t1 t2, t4 ...
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... VALID DATA VALID t2 t10 t6 t5 t11 t13 Note 3 MUST BE: RBUSTMG bit = 0 Parameter if SLOW ARB = 0 opr from the trailing edge of nRD to the ARB from the trailing edge of nWR to the ARB Page 54 DATASHEET Datasheet t7 t8 t12 Note 2 min max units ARB SMSC COM20020I Rev D ...
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... Write cycle for Address Pointer Low Register occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals; Write Cycle SMSC COM20020I Rev D VALID DATA VALID t2 t12 ...
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... Note 3 Parameter min Next )** 4T * ARB from the trailing edge of nWR to the leading edge of the ARB from the trailing edge of nWR to the ARB from the trailing edge of nRD to the ARB Page 56 DATASHEET Datasheet t7 Note 2 t8** t8 t12 max units SMSC COM20020I Rev D ...
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... Data Register requires a minimum of 5T leading edge of the next nRD. Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5T leading edge of nRD. Figure 8.5 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle SMSC COM20020I Rev D VALID t1 t3 Note 3 t10 ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM VALID t10 t8 t6 VALID DATA CASE 2: RBUSTMG bit = 1 Parameter min 4T ARB if SLOW ARB = 0 from the trailing edge of nRD to the ARB from the trailing edge of nWR to the ARB Page 58 DATASHEET Datasheet Note 2 t7 max units *+ 60 100 SMSC COM20020I Rev D ...
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... COM20020 cycles. Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle SMSC COM20020I Rev D VALID ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM VALID t10 t8 VALID DATA CASE 2: RBUSTMG bit = 1 Parameter 4T if SLOW ARB = 0 from the trailing edge of nDS to ARB Page 60 DATASHEET Datasheet t11 Note 2 t9 min max units - *+30 nS ARB 100 nS 30 SMSC COM20020I Rev D ...
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... Register requires a minimum of 5T leading edge of the next nWR. Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data Register requires a minimum of 5T leading edge of nWR. Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle SMSC COM20020I Rev D VALID t10 t6 ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM VALID t10 t8 VALID DATA min Next Time )** 4T ARB 10 30*** SLOW ARB = 0 from the trailing edge of nDS to the leading edge ARB from the trailing edge of nDS to ARB Page 62 DATASHEET Datasheet t11 Note 2 t6 max units SMSC COM20020I Rev D ...
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... Beginning of Last Bit Time to nTXEN High t6 RXIN Active Pulse Width t7 RXIN Period t8 RXIN Inactive Pulse Width Note: Use Only 2.5 Mbps Figure 8.11 - Normal Mode Transmit or Receive Timing (These signals are to and from the hybrid) SMSC COM20020I Rev min -10 850 250 ...
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... Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM t10 t12 t11 Parameter Page 64 DATASHEET Datasheet t13 t8 LAST BIT (400 nS BIT TIME) min typ max units - 200* nS 400 100* nS 100* nS 200 -25 650 750 nS 450 550 nS 10 200* nS 400 SMSC COM20020I Rev D ...
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... Pulse Width*** t2 nINTR High to Next nINTR Low Note period of external XTAL oscillation frequency. XTL Note**: T is period of Data Rate (i.e. at 2.5 Mbps Note***: When the power is turned on measured from stable XTAL oscillation after V DD SMSC COM20020I Rev 1.0V min -200 + - t2 ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM PIN 28L .160-.180 A .090-.120 .013-.021 .026-.032 B 1 .020-.045 C D .485-.495 .450-.456 .390-.430 D 3 .300 .050 BSC F .042-.056 G .042-.048 J .000-.020 R .025-.045 Page 66 DATASHEET Datasheet SMSC COM20020I Rev D ...
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... H 0. 0.50 Basic o θ 0.17 R1 0.08 R2 0.08 ccc ~ ccc ~ Note 1: Controlling Unit: millimeter SMSC COM20020I Rev D Figure 9 Pin TQFP Package Outline MAX ~ 1.6 0.10 0.15 1.40 1.45 9.00 9.20 1 4.50 4. Span Measure from Centerline 2 7.00 7.10 9.00 9.10 1 4.50 4.60 ...
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... RAM initialization sequence to be written. The following discussion describes the function of this bit: During initialization, after the CPU writes the Node ID, the COM20020ID will write "D1"h data to Address 000h and Node-ID to Address 001h of its internal RAM within 6uS. These values are read as part of the diagnostic test ...
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... Tentative-ID register is written, the effect of the old Tentative-ID remains active for a while, which results in an incorrect network map. It can be avoided by a carefully coded software routine, but this requires the programmer to have deep knowledge of how the COM20020ID works. Duplicate-ID is mainly used for generating the Network MAP. This has the same issue as Tentative-ID. ...
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... Setting Pulse nINTR pin EF=1 TA/RI bit Setting Pulse nINTR pin Figure 0.1 - Effect of the EF Bit on the TA/RI Bit Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM Tx/Rx completed prohibition period Tx/Rx completed Page 70 DATASHEET Datasheet SMSC COM20020I Rev D ...
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... ISA Bus ISA Bus AEN nG SA15-SA4 P 12 SD7-SD0 A 8 nIOR nIOW SA2-SA0 3 IRQm nIOCS16 DRQn nDACK TC nREFRESH RESETDRV SMSC COM20020I Rev D LS688x2 12 bit Comparators Q I/O Address Seeting (DIP Switches) P=Q 12 LS245 A 16 bit Bus Transceivers DIR 3 Schmitt-Trigger Buffer Page 71 DATASHEET COM20020 ...
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... If the value read from Register-5 is 0x00 then the part is a COM20020 Rev the value read from Register-5 is 0x80 then the part is a COM20020 Rev D Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 72 DATASHEET Datasheet SMSC COM20020I Rev D ...