COM20020I-HD Standard Microsystems (SMSC), COM20020I-HD Datasheet - Page 4

• Manufacturer Part Number: COM20020I-HD
• Manufacturer: Standard Microsystems (SMSC)

Specifications of COM20020I-HD

• Number Of Transceivers: 1
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Chapter 7
Chapter 8
Chapter 9
Appendix A.................................................................................................................................................. 68
Appendix B -
Appendix C -
List of Figures
Figure 2.1 - Pin Configuration - COM20020I 28-Pin PLCC ............................................................................................7
Figure 2.2 - Pin Configuration - COM20020I 48-Pin TQFP ............................................................................................8
Figure 3.1 - COM20020ID Operation ...........................................................................................................................11
Figure 5.1 – Multiplexed, 8051-Like Bus Interface with RS-485 Interface....................................................................18
Figure 5.2 – Non-Multiplexed, 6801-Like Bus Interface with RS-485 Interface ............................................................19
Figure 5.3 – High Speed CPU Bus Timing – Intel CPU Mode......................................................................................20
Figure 5.4 - COM20020ID Network Using RS-485 Differential Transceivers ...............................................................22
Figure 5.5 – Dipulse Waveform for Data of 1-1-0.........................................................................................................22
Figure 5.6 - Internal Block Diagram..............................................................................................................................24
Figure 6.1 - Sequential Access Operation.....................................................................................................................39
Figure 6.2 - RAM Buffer Packet Configuration .............................................................................................................42
Figure 6.3 – Command Chaining Status Register Queue..............................................................................................44
Figure 8.1 – Multiplexed Bus, 68XX-Like Control Signals; Read Cycle........................................................................53
Figure 8.2 – Multiplexed Bus, 80XX-Like Control Signals; Read Cycle........................................................................54
Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals; Write Cycle.........................................................................55
Figure 8.4 - Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.........................................................................56
Figure 8.5 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................57
Figure 8.6 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................58
Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................59
Figure 8.8 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................60
Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.................................................................61
Figure 8.10 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle ...............................................................62
Figure 8.11 - Normal Mode Transmit or Receive Timing..............................................................................................63
Figure 8.12 - Backplane Mode Transmit or Receive Timing ........................................................................................64
Figure 8.13 - TTL Input Timing on XTAL1 Pin..............................................................................................................65
Figure 8.14 - Reset and Interrupt Timing .....................................................................................................................65
Figure 9.1 - 28 Pin PLCC Package Dimensions...........................................................................................................66
Figure 9.2 - 48 Pin TQFP Package Outline..................................................................................................................67
Figure 0.1 - Effect of the EF Bit on the TA/RI Bit..........................................................................................................70
List of Tables
Table 5.1 - Typical Media.............................................................................................................................................24
Table 6.1 - Read Register Summary............................................................................................................................26
Table 6.2 - Write Register Summary ............................................................................................................................27
Table 6.3 - Status Register ...........................................................................................................................................31
Table 6.4 - Diagnostic Status Register..........................................................................................................................32
Table 6.5 - Command Register.....................................................................................................................................33
Table 6.6 - Address Pointer High Register ....................................................................................................................34
Table 6.7 - Address Pointer Low Register.....................................................................................................................34
Table 6.8 - Sub Address Register .................................................................................................................................34
Table 6.9 - Configuration Register ................................................................................................................................35
Revision 12-05-06
6.8
6.9
7.1
7.2
6.8.1
6.8.2
Improved Diagnostics.................................................................................................................................48
Oscillator ....................................................................................................................................................49
Maximum Guaranteed Ratings* .................................................................................................................50
DC Electrical Characteristics......................................................................................................................50
Normal Results:...................................................................................................................................48
Abnormal Results:...............................................................................................................................48
Operational Description........................................................................................................ 50
Timing Diagrams .................................................................................................................. 53
Package Outlines ................................................................................................................. 66
Example of Interface Circuit Diagram to ISA Bus ............................................................. 71
Software Identification of the COM20020 Rev B, Rev C and Rev D ................................ 72
DATASHEET
Page 4
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I Rev D
Datasheet