COM20020I-HD Standard Microsystems (SMSC), COM20020I-HD Datasheet - Page 45

• Manufacturer Part Number: COM20020I-HD
• Manufacturer: Standard Microsystems (SMSC)

Specifications of COM20020I-HD

• Number Of Transceivers: 1
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
6.5
6.5.1
SMSC COM20020I Rev D
Command Chaining
The Command Chaining operation allows consecutive transmissions and receptions to occur without host
microcontroller intervention.
Through the use of a dual two-level FIFO, commands to be transmitted and received, as well as the status
bits, are pipelined.
In order for the COM20020ID to be compatible with previous SMSC ARCNET device drivers, the device
defaults to the non-chaining mode. In order to take advantage of the Command Chaining operation, the
Command Chaining Mode must be enabled via a logic "1" on bit 6 of the Configuration Register.
In Command Chaining, the Status Register appears as in Figure 6.3.
The following is a list of Command Chaining guidelines for the software programmer. Further detail can be
found in the Transmit Command Chaining and Receive Command Chaining sections.
Transmit Command Chaining
When the processor issues the first "Enable Transmit to Page fnn" command, the COM20020ID responds
in the usual manner by resetting the TA and TMA bits to prepare for the transmission from the specified
page. The TA bit can be used to see if there is currently a transmission pending, but the TA bit is really
meant to be used in the non-chaining mode only. The TTA bits provide the relevant information for the
device in the Command Chaining mode.
In the Command Chaining Mode, at any time after the first command is issued, the processor can issue a
second "Enable Transmit from Page fnn" command. The COM20020ID stores the fact that the second
transmit command was issued, along with the page number.
After the first transmission is completed, the COM20020ID updates the Status Register by setting the TTA
bit, which generates an interrupt. The interrupt service routine should read the Status Register. At this
point, the TTA bit will be found to be a logic "1" and the TMA (Transmit Message Acknowledge) bit will tell
the processor whether the transmission was successful. After reading the Status Register, the "Clear
Transmit Interrupt" command is issued, thus resetting the TTA bit and clearing the interrupt. Note that
only the "Clear Transmit Interrupt" command will clear the TTA bit and the interrupt. It is not necessary,
however, to clear the bit or the interrupt right away because the status of the transmit operation is double
buffered in order to retain the results of the first transmission for analysis by the processor.
information will remain in the Status Register until the "Clear Transmit Interrupt" command is issued. Note
that the interrupt will remain active until the command is issued, and the second interrupt will not occur
until the first interrupt is acknowledged. The COM20020ID guarantees a minimum of 200nS (at EF=1)
interrupt inactive time interval between interrupts. The TMA bit is also double buffered to reflect whether
the appropriate transmission was a success. The TMA bit should only be considered valid after the
corresponding TTA bit has been set to a logic "1". The TMA bit never causes an interrupt.
The device is designed such that the interrupt service routine latency does not affect performance.
Up to two outstanding transmissions and two outstanding receptions can be pending at any given
time. The commands may be given in any order.
Up to two outstanding transmit interrupts and two outstanding receive interrupts are stored by the
device, along with their respective status bits.
The Interrupt Mask bits act on TTA (Rising Transition on Transmitter Available) for transmit operations
and TRI (Rising Transition of Receiver Inhibited) for receive operations. TTA is set upon completion
of a packet transmission only. TRI is set upon completion of a packet reception only. Typically there is
no need to mask the TTA and TRI bits after clearing the interrupt.
The traditional TA and RI bits are still available to reflect the present status of the device.
DATASHEET
Page 45
Revision 12-05-06
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