82V2048DA IDT, Integrated Device Technology Inc, 82V2048DA Datasheet - Page 5

• Manufacturer Part Number: 82V2048DA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2048DA

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table-1 Pin Description (Continued)
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
BPVI0/TDN0
BPVI1/TDN1
BPVI2/TDN2
BPVI3/TDN3
BPVI4/TDN4
BPVI5/TDN5
BPVI6/TDN6
BPVI7/TDN7
TD0/TDP0
TD1/TDP1
TD2/TDP2
TD3/TDP3
TD4/TDP4
TD5/TDP5
TD6/TDP6
TD7/TDP7
TCLK0
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
Name
Type
I
I
TQFP144
108
101
109
102
144
107
100
37
30
80
73
38
31
79
72
36
29
81
74
8
1
7
9
2
Pin No.
PBGA160
N13
B13
D13
N12
B12
D12
N14
B14
D14
L13
L12
L14
N2
D2
B2
N3
D3
B3
N1
D1
B1
L2
L3
L1
TDn: Transmit Data for Channel 0~7
When the device is in Single Rail mode, the NRZ data to be transmitted is input on this pin. Data on TDn is
sampled into the device on the falling edges of TCLKn, and encoded by AMI or B8ZS/HDB3 line code
rules before being transmitted to the line.
BPVIn: Bipolar Violation Insertion for Channel 0~7
Bipolar violation insertion is available in Single Rail mode 2
14) with AMI enabled. A low-to-high transition on this pin will make the next logic one to be transmitted on
TDn the same polarity as the previous pulse, and violate the AMI rule. This is for testing.
TDPn/TDNn: Positive/Negative Transmit Data for Channel 0~7
When the device is in Dual Rail Mode, the NRZ data to be transmitted for positive/negative pulse is input
on this pin. Data on TDPn/TDNn are sampled on the falling edges of TCLKn. The line code in dual rail
mode is as the follow:
Pulling pin TDNn high for more than 16 consecutive TCLK clock cycles will configure the corresponding
channel into Single Rail mode 1 (see
TCLKn: Transmit Clock for Channel 0~7
The clock of 1.544 MHz (for T1 mode) or 2.048 MHz (for E1 mode) for transmit is input on this pin. The
transmit data at TDn/TDPn or TDNn is sampled into the device on the falling edges of TCLKn.
Pulling TCLKn high for more than 16 MCLK cycles, the corresponding transmitter is set in Transmit All
Ones (TAOS) state (when MCLK is clocked). In TAOS state, the TAOS generator adopts MCLK as the
clock reference.
If TCLKn is low, the corresponding transmit channel is set into power down state, while driver output ports
become high-Z.
Different combinations of TCLKn and MCLK result in different transmit mode. It is summarized as the fol-
lows:
Transmit and Receive Digital Data Interface
High/Low
High/Low
Clocked
Clocked
Clocked
MCLK
TDPn
TCLK1 is unavail-
able.
High (≥ 16 MCLK)
0
0
1
1
Low (≥ 64 MCLK) The corresponding transmit channel is set into power down state.
TCLK1 is clocked
Clocked
TCLKn
5
TDNn
Normal operation
Transmit All Ones (TAOS) signals to the line side in the corresponding
transmit channel.
TCLKn is clocked Normal operation
TCLKn is high
(≥ 16 TCLK1)
TCLKn is low
(≥ 64 TCLK1)
The receive path is not affected by the status of TCLK1. When MCLK
is high, all receive paths just slice the incoming data stream. When
MCLK is low, all the receive paths are powered down.
All eight transmitters (TTIPn & TRINGn) will be in high-Z.
0
1
0
1
Table-2 on page 13
Negative Pulse
Description
Positive Pulse
Output Pulse
Space
Space
Transmit All Ones (TAOS) signals to the line side
in the corresponding transmit channel.
Corresponding transmit channel is set into power
down state.
INDUSTRIAL TEMPERATURE RANGES
and
(see Table-2 on page 13 and Table-3 on page
Transmit Mode
Table-3 on page
14).