TXC-03303-ARPQ Transwitch Corporation, TXC-03303-ARPQ Datasheet - Page 5

• Manufacturer Part Number: TXC-03303-ARPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03303-ARPQ

• Lead Free Status / RoHS Status: Compliant

BLOCK DIAGRAM
BLOCK DIAGRAM DESCRIPTION
Figure 1 shows a simplified block diagram of the M13E and its signal leads. In the receive direction, DS3 data
(DS3DR) is clocked into the M13E on positive transitions of the DS3 input clock (DS3CR). The data and clock
signals may be derived from any line interface device such as TranSwitch’s ART, ARTE or DS3LIM-SN, or from
other line circuitry.
The DS3 Frame Sync Block searches for and locks to the DS3 frame, as specified in Bellcore’s TR-TSY-
000499, “Transport System Generic Requirements,” and in ANSI’s T1.107-1988 and supplement T1.107a-
1990. The M13E receiver monitors the DS3 signal for out of frame, loss of signal, a DS3 AIS, DS3 idle signal,
P-bit parity, the state of the X-bits, and loss of clock. The DS3 AIS detection mechanism is software selectable,
with a choice of six detectors. These range from full compliance to T1.107/107a to unframed all ones AIS
detection. Control bits are also provided in memory which allows all, some of, or none of the DS3 alarms to
cause the insertion of AIS into the receive DS1 channels.
In the M13 mode, destuffing from DS3 to DS2 is performed based on the states of the C-bits in the DS3 sub-
frames. If two or three of the C-bits in a subframe are ones, the associated stuff bit is interpreted as being a
stuff bit and is removed from the data stream and discarded.
In the C-bit parity mode, the C-bits are allocated for network performance. The M13E performs Far End Alarm
and Control (FEAC) detection, C-bit parity error detection, and Far End Block Error (FEBE) detection. FEAC
loopback requests and alarm/status information is provided in the memory map. In addition, the states of 14
C-bits (C2, C3, C4, C5, C6, C13, C14, C15, C16, C17, C18, C19, C20, and C21) are provided at a serial inter-
face (CDR), along with an output clock signal (CCKR), framing pulse (CFMR), and data link indicator pulse
(CDCCR). The data link indicator pulse identifies the location of the data link bits, C13, C14, and C15.
CDCCR
OUTDIS
DS3DT
DS3CT
CDT
CCKT
CFMT
CDCCT
DS3DR
DS3CR
CFMR
CCKR
DLEN
TEST
CDR
XCK
Framing/Stuffing
Frame Sync
Loopback
DS3
DS3
Figure 1. M13E TXC-03303 Block Diagram
Destuffing
DS3
TMS
Test Access Port
Framing/Stuffing
TDI
1
7
DS2
TDO
- 5 -
1
Sync/Destuff
TCK
7
Alarm/Status
Control
DS2
TRS
1
1
28
28
Outputs
processor
Input
DS1
DS1
Memory
I/O and
Micro-
Map
Ed. 4, August 1998
TXC-03303
TXC-03303-MB
processor
Interface
Micro-
DR28
DR1
CR28
CR1
S7
S6
S5
DT28
DT1
CT28
CT1
GND
VDD
M13E