LAN91C96-MS Standard Microsystems (SMSC), LAN91C96-MS Datasheet - Page 69

• Manufacturer Part Number: LAN91C96-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN91C96-MS

• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
8.3
SMSC LAN91C96 5v&3v
7
8 a)
1
2
3
4
5
b)
Flow of Events for Receive
ENABLE RECEPTION - By setting the RXEN bit.
SERVICE INTERRUPT - Read the Interrupt
Status Register and determine if RCV INT is set.
The next receive packet is at receive area. (Its
packet number can be read from the FIFO Ports
Register). The software driver can process the
packet by accessing the RX area, and can move
it out to system memory if desired. When
processing is complete the CPU issues the
REMOVE AND RELEASE FROM TOP OF RX
command to have the MMU free up the used
memory and packet number.
SERVICE INTERRUPT – Read Interrupt
Status Register, exit the interrupt service
routine.
Option 1) Release the packet.
Option 2) Check the transmit status in the
EPH STATUS Register, write the packet
number of the current packet to the Packet
Number Register, re-enable TXENA, then
go to step 4 to start the TX sequence again.
S/W DRIVER
DATASHEET
Page 69
a)
b)
A packet is received with matching address.
Memory is requested from MMU. A packet
number is assigned to it. Additional memory is
requested if more pages are needed.
The internal DMA logic generates sequential
addresses and writes the receive words into
memory. The MMU does the sequential to
physical address translation. If overrun, packet
is dropped and memory is released.
When the end of packet is detected, the status
word is placed at the beginning of the receive
packet in memory. Byte count is placed at the
second word. If the CRC checks correctly the
packet number is written into the RX FIFO. The
RX FIFO being not empty causes RCV INT
(interrupt) to be set. If CRC is incorrect the
packet memory is released and no interrupt will
occur.
The MAC generates a TXEMPTY interrupt
upon a completion of a sequence of
enqueued packets.
If a TX failure occurs on any packets, TX
INT is generated and TXENA is cleared,
transmission sequence stops. The packet
number of the failure packet is presented at
the TX FIFO PORTS Register.
CSMA/CD SIDE
Revision 1.0 (10-24-08)