LAN91C96-MS Standard Microsystems (SMSC), LAN91C96-MS Datasheet - Page 87

• Manufacturer Part Number: LAN91C96-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN91C96-MS

• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
9.13.3 Jabber Function
9.13.4 SQE Function
9.14
9.14.1 Receive Drivers
9.14.2 Manchester Decoder and Clock Recovery
9.14.3 Squelch Function
9.14.4 Reverse Polarity Function
SMSC LAN91C96 5v&3v
This integrated function prevents the DTE from locking into a continuous transmit state. In 10BASE-T
mode, if transmission continues beyond the specified time limit, the jabber function inhibits further
transmission and asserts the collision indicator nCOLL. The limits for jabber transmission are 20 to 15 ms
in 10BASE-T mode. In the AUI mode, the jabber function is performed by the external transceiver.
In the 10BASE-T mode, the PHY supports the signal quality error (SQE) function. At the end of a
transmission, the PHY asserts the nCOLL signal for 10+/-5 bit times beginning 0.6 to 1.6ms after the last
positive transition of a transmitted frame. In the AUI mode, the SQE function is performed by the external
transceiver.
Receive Functions
Differential signals received off the twisted-pair network or AUI cable are directed to the internal clock
recovery circuit prior to being decoded for the MAC.
The PHY performs timing recovery and Manchester decoding of incoming differential signals in 10BASE-T
or AUI modes, with its built-in phase-lock loop (PLL). The decoded (NRZ) data, RXD, and the recovered
clock, RXCLK, becomes available to the MAC, typically within 9 bit times (5 for AUI) after the assertion of
nCRS. The receive clock, RXCLK, is phase-locked to the transmit clock in the absence of a received
signal (idle).
The integrated smart squelch circuit employs a combination of amplitude and timing measurements to
determine the validity of data received off the network. It prevents noise at the differential inputs from
falsely triggering the decoder in the absence of valid data or link test pulses. Signal levels below 300mV
(180mV for AUI) or pulse widths less than 15ns at the differential inputs are rejected. Signals above
585mV (300mV for AUI) and pulse widths greater than 30ns will be accepted. When using the extended
cable mode with 10BASE-T media which extends beyond the standard limit of 100 meters, the squelch
level can optionally be set to reject signals below 180mV and accept signals above 300mV. If the input
signal exceeds the squelch requirements, the carrier sense output, nCRS, is asserted.
In the 10BASE-T mode, the PHY monitors for receiver polarity reversal due to crossed wires and corrects
by reversing the signal internally.
DATASHEET
Page 87
Revision 1.0 (10-24-08)