AM79C976KI AMD (ADVANCED MICRO DEVICES), AM79C976KI Datasheet - Page 141

• Manufacturer Part Number: AM79C976KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C976KI

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Not Compliant

CTRL0: Control0 Register
Offset 068h
This register contains several miscellaneous control
bits. Each byte of this register controls a single func-
tion. It is not necessary to do a read-modify-write oper-
ation to change a function’s settings if only a single byte
of the register is written.
9/14/00
31-25
17-16
15-12
23:18
Bit
24
SRAM_TYPE
BSWP
Name
RES
RES
RES
Reserved locations. Written as zeros and read as undefined.
Byte Swap. This bit is used to choose between big and little Endian modes of operation. When
BSWP is set to a 1, big Endian mode is selected. When BSWP is set to 0, little Endian mode is
selected.
When big Endian mode is selected, the Am79C976 controller will swap the order of bytes on the
AD bus during a data phase on accesses to the FIFOs only. Specifically, AD[31:24] becomes Byte
0, AD[23:16] becomes Byte 1, AD[15:8] becomes Byte 2, and AD[7:0] becomes Byte 3 when big
Endian mode is selected. When little Endian mode is selected, the order of bytes on the AD bus
during a data phase is: AD[31:24] is Byte 3, AD[23:16] is Byte 2, AD[15:8] is Byte 1, and AD[7:0]
is Byte 0.
Byte swap only affects data transfers that involve the FIFOs. Initialization block transfers are not
affected by the setting of the BSWP bit. Descriptor transfers are not affected by the setting of the
BSWP bit. RDP, RAP, BDP and PCI configuration space accesses are not affected by the setting
of the BSWP bit. Address PROM transfers are not affected by the setting of the BSWP bit.
Expansion ROM accesses are not affected by the setting of the BSWP bit.
Note that the byte ordering of the PCI bus is defined to be little Endian. BSWP should not be set
to 1 when the Am79C976 controller is used in a PCI bus application.
This bit is an alias of CSR3, bit 2.
Reserved locations. Written as zeros and read as undefined.
SSRAM Type. This field must be set up to indicate the type of external SSRAM that is connected
to the external memory interface.
Reserved locations. Written as zeros and read as undefined.
Table 46.
P R E L I M I N A R Y
SRAM_TYPE[1:0]
CTRL0: Control0 Register
Am79C976
00
01
10
11
All bits in this register are set to their default values by
H_RESET. All bits are also set to their default values
before EEPROM data are loaded or after an EEPROM
read failure.
The default value for all bits except for bits 11:8
(ROMTMG) is 0. The default value for the ROMTMG
field is 1001b.
Description
External Memory Type
Pipelined Burst
Reserved
Reserved
ZBT
141