AM79C976KI AMD (ADVANCED MICRO DEVICES), AM79C976KI Datasheet - Page 45

• Manufacturer Part Number: AM79C976KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C976KI

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Not Compliant

Basic Burst Write Transfer
The Am79C976 controller supports burst mode for all
bus master write operations. To allow burst transfers in
descriptor write operations, the Am79C976 controller
must be programmed to use SWSTYLE 3, 4, or 5
(BCR20, bits 7-0).
The controller uses the following rules to determine
whether to use the PCI Memory Write (MW) command
or the Memory Write and Invalidate (MWI) command
for burst write transfers.
The Receive FIFO threshold should be greater than or
equal to the cache line size to maximize the use of the
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— When a transfer starts on a cache line boundary,
— When a transfer does not start on a cache line
— Stop the MWI transfer at a cache line boundary
and there is at least a cache line of data to trans-
fer, use MWI.
boundary, use MW. (The external PCI bridge
should stop the transfer at the cache line bound-
ary if it can make good use of the MWI com-
mand.)
if there is less than 1 cache line of data left to
transfer.
DEVSEL
FRAME
TRDY
C/BE
IRDY
REQ
GNT
CLK
PAR
AD
1
DEVSEL is sampled
2
Figure 13. Non-Burst Write Transfer
ADDR
0111
3
P R E L I M I N A R Y
PAR
4
Am79C976
DATA
BE
5
PAR
MWI command. If the PCI bridge stops a transfer, the
Am79C976 device waits until the FIFO threshold con-
ditions are met before resuming the transfer.
AD[1:0] will both be 0 indicating a linear burst order.
The byte enable signals indicate which byte lanes have
valid data.
The Am79C976 controller will always perform a single
burst write transaction per bus mastership period,
where transaction is defined as one address phase and
one or multiple data phases. The Am79C976 controller
supports zero wait state write cycles when using the
Memory Write command. When using Memory Write
and Invalidate commands, the device may insert IRDY
wait states anywhere in the transaction.
The device asserts IRDY immediately after the address
phase and at the same time starts sampling DEVSEL.
FRAME is deasserted when the next-to-last data
phase is completed.
Figure 14 shows a typical burst write access. The
Am79C976 controller arbitrates for the bus, is granted
access, and writes four 32-bit words (DWords) to the
system memory and then releases the bus. In this ex-
During the address phase of a burst write transfer
6
7
ADDR
0111
8
DATA
PAR
BE
9
PAR
10
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