CY7C955-NC Cypress Semiconductor Corp, CY7C955-NC Datasheet - Page 58

• Manufacturer Part Number: CY7C955-NC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C955-NC

• Lead Free Status / RoHS Status: Not Compliant

REG
7
6
5
4
3
2
1
0
TGFCE[3:0]
This is the Transmit Generic Flow Control Enable register. Each bit of this register corresponds to a bit in the GFC field of the
transmitted ATM cell headers. If TGFCE[x] is set HIGH, bit x of the GFC field in the transmitted ATM cell headers will be using
the bit value collected from the TGFC (pin 52) pin (see description of Drop Side Transmit Interface). If TGFCE[x] is LOW, bit x
will be derived from either TDAT (if transmit FIFO has at least one cell available) or from the Idle/Unassigned header register
(if transmit FIFO has less than 1 cell available).
FSEN
This is the fix stuff enable bit. This bit will only affect the STS 1 frame.
0:
1:
H4INSB
This bit controls the contents of H4 byte.
0:
1:
FIXBYTE[1:0]
This register holds the number to be used in the fixed byte columns.
11:
10:
01:
00:
BIT POSITION
No stuffing is performed.
Column 30 and 59 of the STS 1 frame contains fix stuff bytes. The contents for the fix stuff byte is controlled by
FIXBYTE[1:0] (Reg 67H, bit 0 1).
H4 byte represents the cell indicator offset value.
H4 byte is set to 00H.
FFH is inserted into the fixed byte columns.
AAH is inserted into the fixed byte columns.
55H is inserted into the fixed byte columns.
00H is inserted into the fixed byte columns.
67H
Transmit ATM Cell Processor Transmit Configuration Register
TGFCE[3]
TGFCE[2]
TGFCE[1]
TGFCE[0]
FSEN
H4INSB
FIXBYTE[1]
FIXBYTE[0]
PRELIMINARY
NAME
58
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
READ/WRITE
0
0
0
0
1
0
0
0
CY7C955
DEFAULT