MC145423EJR2 Freescale, MC145423EJR2 Datasheet - Page 7

• Manufacturer Part Number: MC145423EJR2
• Manufacturer: Freescale

Specifications of MC145423EJR2

• Number Of Transmitters: 1
• Number Of Receivers: 1
• Power Supply Requirement: Single
• Package Type: TSSOP
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Lead Free Status / RoHS Status: Compliant

MC145423
MC145423 UDLT-3 PIN STATES FOR UDLT-1 SLAVE MODE (continued)
MC145423 UDLT-3 PIN STATES FOR UDLT-1 MASTER MODE
16
Pin
No.
Pin
No.
23
24
25
26
27
28
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
MASTER/
FRAME 10/20
SLAVE
MC145423
Name
BCLK
SE/(Mu/A)
EN2-TE2/
SIE/B1B2
RE2/
V DD
LO2
LO1
Pin
SDCLK
TRI/SQ
Rx
MC145423
Name
SDO1
SDO2
MOD
SDI1
SDI2
V SS
V ref
Pin
VD
PD
LB
Tx
LI
Output
Output
Output
Power
In/out
Input
Input
Don’t Care High Impedance High Impedance High Impedance High Impedance High Impedance
Analog
Output
Output
Output
Output
Power
In/out
Input
Input
Input
Input
Input
Input
Input
Input
Input
Ref
Modulator
Modulator
128 kHz
Freescale Semiconductor, Inc.
Normal
BCLK =
64 kbps
Data In
UDLT-1 Slave Mode
8 kbps Data Out 8 kbps Data Out High Impedance 8 kbps Data Out High Impedance
8 kbps Data Out 8 kbps Data Out High Impedance 8 kbps Data Out High Impedance
Out
Out
8 kbps Data In
8 kbps Data In
+V
Power Supply
AGND V DD /2
For More Information On This Product,
SIE Digital In
1
Digital out
Analog In
Data Out
Powered-Up
64 kbps
Normal
Gnd
1
0
1
1
0
Go to: www.freescale.com
TELECOMMUNICATIONS
Don’t Care
Modulator
Modulator
BCLK = 0
LB Low
UDLT-1 Master Mode
Out
Out
+V
1
8 kbps Data In
8 kbps Data In
Power Supply
AGND V DD /2
Powered-Up
SIE Digital In
Don’t Care
Digital out
Data Out
LB Low
64 kbps
Gnd
0
0
1
1
0
Burst Rec’d
LO2 = LO1
LO1 = LO2
Don’t Care
No Valid
128 kHz
BCLK =
+V
1
TONE = 0, Off
High Impedance
Power Supply
State Latched
State Latched
State Latched
State Latched
AGND V DD /2
SIE Digital In
UDLT-1 Slave Mode Powered-Down
Analog In
Data Out
SE Low
64 kbps
Gnd
Burst Rec’d
0
0
0
LO2 = LO1
LO1 = LO2
Don’t Care
128 kHz
BCLK =
Valid
+V
1
8 kbps Data In
8 kbps Data In
Power Supply
AGND V DD /2
SIE Digital In
SDO1, SDO2, VD
Don’t Care
Digital out
Analog In
Data Out
Normal
64 kbps
Burst Rec’d
LO2 = LO1
LO1 = LO2
Gnd
Don’t Care
UDLT-1 Master Mode
No Valid
128 kHz
0
1
0
0
BCLK =
Powered-Down
+V
LB, PD
1
TONE = 1, On
SE
High Impedance
Power Supply
AGND V DD /2
State Latched
State Latched
State Latched
SIE Digital In
Don’t Care
Burst Rec’d
Analog In
Data Out
LO2 = LO1
LO1 = LO2
Don’t Care
SE Low
64 kbps
128 kHz
BCLK =
Gnd
Valid
0
0
0
+V
1
Figure 6. SE
TELECOMMU
INTERNAL
t h
t dly1
PREVIO