SI3011-F-FSR Silicon Laboratories Inc, SI3011-F-FSR Datasheet - Page 28

• Manufacturer Part Number: SI3011-F-FSR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3011-F-FSR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Si3050 + Si3011
1. When ring validation is enabled, the status bit seen
2. The RDTI interrupt fires when a validated ring
3. The INT pin follows the RDTI bit with configurable
4. The RGDT pin can be configured to follow the
5.20. Ringer Impedance
The ring detector in a typical DAA is ac coupled to the
line with a large 1 µF, 250 V decoupling capacitor. The
ring detector on the Si3011 is resistively coupled to the
line. This coupling produces a high ringer impedance to
the line of approximately 20 M  to meet FCC and
TBR21 specifications.
5.21. Pulse Dialing
Pulse dialing is accomplished by going off- and on-hook
to generate make and break pulses. The nominal rate is
10 pulses per second. Some countries have strict
specifications for pulse fidelity including make and
break times, make resistance, and rise and fall times. In
a traditional, solid-state dc holding circuit, there are a
number of issues in meeting these requirements.
The Si3050 dc holding circuit has active control of the
on- and off-hook transients to maintain pulse dialing
fidelity.
To ensure proper operation of the DAA during pulse
dialing, disable the automatic resistor calibration that is
performed each time the DAA enters the off-hook state
by setting the RCALD bit (Register 25, bit 5).
5.22. Receive Overload Detection
The Voice DAA chipset is capable of monitoring and
reporting receive overload conditions on the line. Billing
tones, parallel phone off-hook events, polarity reversals
and other disturbances on the line may trigger multiple
levels of overload detection as described below.
Transient events less than 1.1 V
28
in the RDT read-only bit (r5.2), represents the
detected envelope of the ring. The ring validation
parameters are configurable so that this envelope
may remain high throughout a distinctive-ring
sequence.
occurs. If RDI is zero (default), the interrupt occurs
on the rising edge of RDT. If RDI is set, the interrupt
occurs on both rising and falling edges of RDT.
polarity.
ringing signal envelope detected by the ring
validation circuit by setting RFWE to 0. If RFWE is
set to 1, the RGDT pin follows an unqualified ring
detect one-shot signal initiated by a ring-threshold
crossing and terminated by a fixed counter timeout
of approximately 5 seconds. (This information is
shown in Register 18).
PK
on the line are
Rev. 1.11
filtered out by the low-pass digital filter on the
Si3050+Si3011 chipset. The ROV and ROVI bits are set
when the received signal is greater than 1.1 V
bits will continue to indicate an overload condition until a
zero is written to clear. The OVL mirrors the function of
the ROV and ROVI bits but it automatically clears after
the overload condition has been removed. When the
OVL
auto-calibration sequence that must complete before
data can be transmitted. An external interrupt can
optionally be triggered by the ROVI bit by setting the
ROVM and INTE bits.
Certain events such as billing tones can be sufficiently
large to disrupt the line-derived power supply of the
Voice DAA line side device. To ensure that the device
maintains the off-hook line state during these events,
the BTE bit should be set. If such an event occurs while
the BTE bit is set, the BTD and BTDI bits will be
asserted. A zero must be written to the BTE bit to clear
the BTD and BTDI bits. An external interrupt can
optionally be triggered by the BTDI bit by setting the
BTDM and INTE bits.
In the event that a line disturbance causes the loop
current to collapse below the minimum required
operating current of the Voice DAA, the DOD and DODI
bits will be set. An external interrupt can optionally be
triggered by the DODI bit by setting the DODM and
INTE bits.
5.23. Billing Tone Filter (Optional)
Optionally, a billing tone filter may be inserted between
the line and the voice DAA to minimize disruptions
caused by large billing tones. The notch filter design
requires two notches, one at 12 kHz and one at 16 kHz.
Because these components are expensive and few
countries utilize billing tones, this filter is typically placed
in an external dongle or added as a population option.
Figure 23 shows a billing tone filter example. Table 16
gives the component values.
L1 must carry the entire loop current. The series
resistance of the inductors is important to achieve a
narrow and deep notch. This design has more than
25 dB of attenuation at both 12 kHz and 16 kHz.
bit
returns
to
0,
the
DAA
initiates
PK
. Both
an