ICS1892Y-14LF IDT, Integrated Device Technology Inc, ICS1892Y-14LF Datasheet - Page 113

• Manufacturer Part Number: ICS1892Y-14LF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS1892Y-14LF

• Lead Free Status / RoHS Status: Compliant

9.2.4.2 MAC/Repeater Interface Pins for 100M Symbol Interface
ICS1892, Rev. D, 2/26/01
Table 9-7
Table 9-7. MAC/Repeater Interface Pins: 100M Symbol Interface
COL
CRS
MDC
MDIO
RXCLK
MII Pin
Name
ICS1892
lists the MAC/Repeater Interface pin descriptions for the 100M Symbol Interface.
–
SCRS
MDC
MDIO
SRCLK
Symbol
Name
100M
Pin
No.
Pin
49
50
31
30
37
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
Connect
Output
Output
Input/
Type
Input
Pin
No
Collision (Detect).
For the 100M Symbol Interface, this pin is a no connect. For
more information, see
Symbol Carrier Sense.
This pin’s description is the same as that given in
Management Data Clock.
This pin’s description is the same as that given in
Management Data Input/Output.
This pin’s description is the same as that given in
Symbol Receive Clock.
The ICS1892 sources the SRCLK to the MAC/repeater. The
ICS1892 uses SRCLK to synchronize the signals on the
SRD0–4 pins. The following table contrasts the behavior on the
SRCLK pin when the mode for the ICS1892 is either 10Base-T
or 100Base-TX.
Note: The signal on the SRCLK pin is conditioned by RXTRI,
The SRCLK frequency is 25
MHz.
The ICS1892 generates
SRCLK from the MDI data
stream while there is a valid link
(that is, either data or IDLEs).
In the absence of a link, the
ICS1892 uses the REFIN clock
to generate the SRCLK.
The ICS1892 switches
between clock sources during
the period between when
SCRS is being asserted and
RXDV is being asserted. While
the ICS1892 is bringing up a
link, a clock phase change of
up to 360 degrees can occur.
113
that is, the Receive (Interface) Tri-State signal.
100Base-TX
Chapter 9 Pin Diagram, Listings, and Descriptions
Table
Pin Description
6-1.
February 26, 2001
Table
Table
Table
9-6.
9-6.
9-6.