1892Y-14LFT IDT, Integrated Device Technology Inc, 1892Y-14LFT Datasheet - Page 18

• Manufacturer Part Number: 1892Y-14LFT
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 1892Y-14LFT

• Lead Free Status / RoHS Status: Compliant

5.1 Reset Operations
5.1.1 General Reset Operations
5.1.1.1 Entering Reset
5.1.1.2 Exiting Reset
5.1.1.3 Hot Insertion
ICS1892, Rev. D, 2/26/01
This section first discusses reset operations in general and then specific ways in which the ICS1892 can be
configured for various reset options.
The following reset operations apply to all the specific ways in which the ICS1892 can be reset, which are
discussed in
When the ICS1892 enters a reset condition (either through hardware, power-on reset, or software), it does
the following:
1. Isolates the MAC/Repeater Interface input pins
2. Drives all MAC/Repeater Interface output pins low
3. Tri-states the signals on its Twisted-Pair Transmit pins (TP_TXP and TP_TXN)
4. Initializes all its internal modules and state machines to their default states
5. Enters the power-down state
6. Initializes all internal latching low (LL), latching high (LH), and latching maximum (LMX) Management
When the ICS1892 exits a reset condition, it does the following:
1. Exits the power-down state
2. Latches the Serial Management Port Address of the ICS1892 into the Extended Control Register, bits
3. Enables all its internal modules and state machines
4. Sets all Management Register bits to either (1) their default values or (2) the values specified by their
5. Enables the Twisted-Pair Transmit pins (TP_TXP and TP_TXN)
6. Resynchronizes both its Transmit and Receive Phase-Locked Loops, which provide its transmit clock
7. Releases all MAC/Repeater Interface pins, which takes a maximum of 640 ns after the reset condition
As with the ICS 1890, the ICS1892 reset design supports ‘hot insertion’ of its MII. (That is, the ICS1892 can
connect its MAC/Repeater Interface to a MAC/repeater while power is already applied to the
MAC/repeater.)
Register bits to their default values
16.10:6. [See
associated ICS1892 input pins, as determined by the HW/SW pin
(TXCLK) and receive clock (RXCLK)
is removed
ICS1892 Data Sheet
Section 5.1.2, “Specific Reset
Section 8.11.3, “PHY Address (bits
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
Operations”.
18
16.10:6)”.]
Chapter 5 Operating Modes Overview
February 26, 2001