IDT82V1671AJ IDT, Integrated Device Technology Inc, IDT82V1671AJ Datasheet - Page 61

• Manufacturer Part Number: IDT82V1671AJ
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V1671AJ

• Number Of Channels: 4
• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: PLCC
• Operating Temperature Classification: Industrial
• Pin Count: 28
• Mounting: Surface Mount
• Operating Current: 95mA
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Lead Free Status / RoHS Status: Compliant

data is stored in the FSK-RAM that is shared by all four channels. The
FSK-RAM consists of 32 words, 16 bits (two bytes) per word. They are
addressed by the FSK-RAM commands.
FSK-RAM to be accessed. In both MPI and GCI modes, when
addressing a FSK-RAM word, 16 bits will be written to or read out from
this word with MSB first.
local registers except the data is twice as long. When executing a FSK-
RAM command, the CODEC automatically counts down from the
address specified in the command (b[4:0]) to the address of '00000',
resulting in total b[4:0]+1 words of FSK-RAM being addressed. As the
data written to or read out from the FSK-RAM is 16-bit (two-byte) wide,
total (b[4:0]+1)∗ 2 bytes of data will follow a FSK-RAM command. Refer
to
for more information.
local registers except the data is twice as long (the data for the FSK-
RAM is 16-bit wide while the data for local registers is 8-bit wide). Refer
to
for more information.
5.2.5
and each block consists of 8 words. So, there are total 96 words per
channel. The coefficient RAM mapping is shown in
RSLIC & CODEC CHIPSET
“5.4.1.4 Example of Programming the FSK-RAM via MPI” on page 84
“5.4.2.4 Example of Programming the FSK-RAM via GCI” on page 86
The b[4:0] bits in a FSK-RAM command specify a location in the
• MPI Mode
In MPI mode, the FSK-RAM is addressed in a similar manner as the
• GCI Mode
In GCI mode, the FSK-RAM is addressed in a similar manner as the
The Coe-RAM (Coefficient RAM) consists of 12 blocks per channel,
ADDRESSING THE COE-RAM
Table - 23.
61
bits (or two 8-bit bytes) are needed to fill one word with MSB first, but the
first two bits (MSB) will be ignored. When being read, each Coe-RAM
word will output 16 bits with MSB first, but the first two bits are
meaningless.
Enable command that specifies which channel(s) to be accessed.
block of the Coe-RAM for the specified channel(s) will be addressed.
The CODEC automatically counts down from the highest address to the
lowest address of the specified block. So one block (consists of eight
words) can be addressed by one Coe-RAM Command.
Coe-RAM can be stopped by the CS pin at any time. When the CS pin
changes from low to high, the operation on the current word and the next
adjacent words will be aborted. But the operations that are
accomplished before the CS pin goes high have been executed.
on page 84
pin) and the b4 bit in Program Start byte specify a channel of which the
Coe-RAM will be addressed. The address (b[4:0]) in the Coe-RAM
Command locates a block of the Coe-RAM. When executing a Coe-
RAM Command, all eight words in the block will be read/written
automatically, with the highest order word first.
can not be stopped once a Coe-RAM command is initiated.
on page 85
Each word in Coe-RAM is 14-bit wide. To write a Coe-RAM word, 16
• MPI Mode
In MPI mode, the Coe-RAM commands always follow the Channel
The address (b[4:0]) in the Coe-RAM commands indicates which
In MPI mode, the procedure of reading/writing words from/to the
See
• GCI Mode
In GCI mode, both the location of time slot (determined by S1 and S0
In GCI mode, the procedure of the consecutive adjacent addressing
See
“5.4.1.3 Example of Programming the Coefficient-RAM via MPI”
“5.4.2.3 Example of Programming the Coefficient-RAM via GCI”
for detailed information.
for details.
IDT82V1671/IDT82V1671A, IDT82V1074