PIC12F1822-E/P Microchip Technology, PIC12F1822-E/P Datasheet - Page 281

• Manufacturer Part Number: PIC12F1822-E/P
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 P
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12F1822-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 25-2:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note
R/C/HS-0/0
WCOL
1:
2:
3:
4:
5:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF
register.
When enabled, these pins must be properly configured as input or output.
When enabled, the SDA and SCL pins must be configured as inputs.
SSP1ADD values of 0, 1 or 2 are not supported for I
SSP1ADD value of ‘0’ is not supported. Use SSP1M = 0000 instead.
WCOL: Write Collision Detect bit
Master mode:
1 = A write to the SSP1BUF register was attempted while the I
0 = No collision
Slave mode:
1 = The SSP1BUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
SSP1OV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSP1BUF register is still holding the previous data. In case of overflow, the data in SSP1SR
0 = No overflow
In I
1 = A byte is received while the SSP1BUF register is still holding the previous byte. SSP1OV is a “don’t care” in Transmit
0 = No overflow
SSP1EN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I
SCL release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I
Unused in this mode
SSP1M<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0010 = SPI Master mode, clock = F
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0110 = I
0111 = I
1000 = I
1001 = Reserved
1010 = SPI Master mode, clock = F
1011 = I
1100 = Reserved
1101 = Reserved
1110 = I
1111 = I
R/C/HS-0/0
2
2
2
2
SSP1OV
C mode:
C mode:
C Slave mode:
C Master mode:
is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSP1BUF, even if only transmitting
data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is
initiated by writing to the SSP1BUF register (must be cleared in software).
mode (must be cleared in software).
SSP1CON1: SSP1 CONTROL REGISTER 1
2
2
2
2
2
2
C Slave mode, 7-bit address
C Slave mode, 10-bit address
C Master mode, clock = F
C firmware controlled Master mode (Slave Idle)
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
SSP1EN
R/W-0/0
PIC12F/LF1822/PIC16F/LF1823
OSC
OSC
OSC
OSC
OSC
R/W-0/0
/4
/16
/64
/(4 * (SSP1ADD+1))
/ (4 * (SSP1ADD+1))
(1)
CKP
Preliminary
2
C Mode.
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Bit is set by hardware
R/W-0/0
(5)
(4)
2
C conditions were not valid for a transmission to be started
R/W-0/0
SSP1M<3:0>
C = User cleared
R/W-0/0
(2)
(3)
DS41413B-page 281
R/W-0/0
bit 0