PIC16LC63-04/SO Microchip Technology, PIC16LC63-04/SO Datasheet
PIC16LC63-04/SO
Specifications of PIC16LC63-04/SO
Related parts for PIC16LC63-04/SO
PIC16LC63-04/SO Summary of contents
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... Yes Interrupt Sources 3 7 Sink/Source Current (mA) 25/20 25/25 25/25 25/25 25/25 1997 Microchip Technology Inc. PIC16C6X • Low-power, high-speed CMOS EPROM/ROM technology • Fully static design • Wide operating voltage range: 2.5V to 6.0V • Commercial, Industrial, and Extended temperature ranges • ...
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... RB2 RA5/ RB1 RE0/ RB0/INT 32 RE1/ RE2/ RD7/PSP7 RD6/PSP6 OSC1/CLKIN 13 28 RD5/PSP5 OSC2/CLKOUT 14 27 RD4/PSP4 15 26 RC7/RX/DT RC1/T1OSI/CCP2 16 25 RC6/TX/CK RC2/CCP1 17 24 RC5/SDO RC3/SCK/SCL 18 23 RC4/SDI/SDA RD0/PSP0 19 22 RD3/PSP3 RD1/PSP1 20 21 RD2/PSP2 PIC16C65 PIC16C65A PIC16CR65 PIC16C67 1997 Microchip Technology Inc. ...
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... RC7/RX/ RD4/PSP4 RD5/PSP5 3 31 PIC16C65 4 30 RD6/PSP6 5 29 RD7/PSP7 PIC16C65A PIC16CR65 8 26 RB0/INT RB1 9 PIC16C67 RB2 RB3 11 23 1997 Microchip Technology Inc. PLCC RA4/T0CKI NC 33 RA5/SS 32 RC0/T1OSI/T1CKI RE0/RD 31 OSC2/CLKOUT RE1/WR 30 OSC1/CLKIN RE2/ RE2/CS OSC1/CLKIN 26 RE1/WR OSC2/CLKOUT 25 RE0/RD RC0/T1OSI/T1CKI 24 RA5/ RA4/T0CKI PLCC ...
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... However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document. DS30234D-page 4 1997 Microchip Technology Inc. ...
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... Serial Peripheral Interface (SPI the two-wire Inter-Integrated Circuit (I versal Synchronous Asynchronous Receiver Transmit- 1997 Microchip Technology Inc. ter (USART) is also known as a Serial Communications Interface or SCI. An 8-bit Parallel Slave Port is also pro- vided. The PIC16C6X device family has special features to ...
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... TMR1, TMR2 TMR2 TMR2 SPI/I C, SPI/I C, SPI/I C, USART USART USART Yes — Yes 2.5-6.0 2.5-6.0 2.5-6.0 Yes Yes Yes Yes Yes Yes 40-pin DIP; 28-pin SDIP, 40-pin DIP; 44-pin SOIC 44-pin PLCC, PLCC, MQFP, MQFP, TQFP TQFP 1997 Microchip Technology Inc. ...
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... EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before produc- tion shipments are available. Please contact your local Microchip Technology sales office for more details. 2.4 Serialized Quick-Turnaround Production (SQTP Microchip offers a unique programming service where a few user-defi ...
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... PIC16C6X NOTES: DS30234D-page 8 1997 Microchip Technology Inc. ...
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... This symmetrical nature and lack of “special optimal situations” makes programming with the PIC16CXX simple yet efficient, thus significantly reducing the learning curve. 1997 Microchip Technology Inc. PIC16C6X The PIC16CXX device contains an 8-bit ALU and work- ing register (W). The ALU is a general purpose arith- metic unit ...
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... Registers (1) 9 RAM Addr Addr MUX Indirect 7 Direct Addr 8 Addr FSR reg STATUS reg 3 MUX Power-up Timer Oscillator Start-up Timer ALU Power-on 8 Reset Watchdog W reg Timer Timer0 MCLR PORTA RA0 RA1 RA2 RA3 RA4/T0CKI PORTB RB0/INT RB7:RB1 1997 Microchip Technology Inc. ...
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... Note 1: Higher order bits are from the STATUS register. 2: PORTD, PORTE and the Parallel Slave Port are not available on the PIC16C62/62A/R62. 3: Brown-out Reset is not available on the PIC16C62/64. 4: Pin functions T1OSI and T1OSO are swapped on the PIC16C62/64. 1997 Microchip Technology Inc. 8 Data Bus RAM ...
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... Port Timer2 CCP1 CCP2 PORTA RA0 RA1 RA2 RA3 RA4/T0CKI RA5/SS PORTB RB0/INT RB7:RB1 PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 PORTE RE0/RD RE1/WR RE2/CS (Note 2) 1997 Microchip Technology Inc. ...
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... OSC2/CLKOUT MCLR Timer0 Timer1 Synchronous USART Serial Port Note 1: Higher order bits are from the STATUS register. 2: PORTD, PORTE and the Parallel Slave Port are not available on the PIC16C66. 1997 Microchip Technology Inc. 8 Data Bus RAM File (13-bit) Registers 368 x 8 (1) ...
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... Interrupt on change pin. Serial programming clock. (3) I/O TTL/ST Interrupt on change pin. Serial programming data. P — Ground reference for logic and I/O pins. P — Positive supply for logic and I/O pins. I/O = input/output P = power TTL = TTL input ST = Schmitt Trigger input 1997 Microchip Technology Inc. ...
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... This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 4: This buffer is a Schmitt Trigger input when configured as the external interrupt. 5: This buffer is a Schmitt Trigger input when used in serial programming mode. 1997 Microchip Technology Inc. Buffer Description ...
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... RC5 can also be the SPI Data Out (SPI mode). 44 I/O ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock 1 I/O ST RC7 can also be the USART Asynchronous Receive or Synchronous Data I/O = input/output P = power TTL = TTL input ST = Schmitt Trigger input (1) (1) ( modes mode). (2) (2) . (2) (2) . 1997 Microchip Technology Inc ...
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... This buffer is a Schmitt Trigger input when used in serial programming mode. 6: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 1997 Microchip Technology Inc. TQFP Pin ...
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... Q4 (destination write PC+1 Fetch INST (PC+1) Execute INST (PC) Tcy1 Tcy2 Tcy3 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch Internal Phase Clock PC+2 Fetch INST (PC+2) Execute INST (PC+1) Tcy4 Tcy5 Flush Fetch SUB_1 Execute SUB_1 1997 Microchip Technology Inc. ...
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... PIC16C61 PROGRAM MEMORY MAP AND STACK PC<12:0> 13 CALL, RETURN RETFIE, RETLW Stack Level 1 Stack Level 8 Reset Vector Peripheral Interrupt Vector On-chip Program Memory 1997 Microchip Technology Inc. FIGURE 4-2: CALL, RETURN RETFIE, RETLW 0000h-03FFh 0000h-07FFh 0000h-07FFh 0000h-07FFh 0000h-0FFFh 0000h-0FFFh 0000h-07FFh 0000h-07FFh ...
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... OPTION 81h PCL PCL 82h STATUS STATUS 83h FSR FSR 84h PORTA TRISA 85h PORTB TRISB 86h 87h 88h 89h PCLATH PCLATH 8Ah INTCON INTCON 8Bh 8Ch General Mapped (2) Purpose in Bank 0 Register AFh B0h FFh Bank 0 Bank 1 1997 Microchip Technology Inc. ...
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... General Purpose Register 7Fh Bank 1 Bank 0 Unimplemented data memory location; read as '0'. Note 1: Not a physical register. 2: PORTD and PORTE are not available on the PIC16C62/62A/R62. 1997 Microchip Technology Inc. FIGURE 4-7: File Address File Address 80h INDF 00h TMR0 81h 01h 82h ...
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... Purpose 118h 198h Register 119h 199h 16 Bytes 11Ah 19Ah 11Bh 19Bh 11Ch 19Ch 11Dh 19Dh 11Eh 19Eh 11Fh 19Fh 120h 1A0h General Purpose Register 80 Bytes 1EFh 16Fh 1F0h accesses 170h 70h-7Fh in Bank 0 17Fh 1FFh Bank 3 1997 Microchip Technology Inc. ...
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... Other (non power-up) resets include external reset through MCLR and the Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C61, always maintain these bits clear. 1997 Microchip Technology Inc. The special function registers can be classified into two sets (core and peripheral). The registers associated with the “ ...
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... T2CKPS1 T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu SSPM1 SSPM0 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M1 CCP1M0 --00 0000 --00 0000 — — 1997 Microchip Technology Inc. ...
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... The BOR bit is reserved on the PIC16C62, always maintain this bit set. 5: The IRP and RP1 bits are reserved on the PIC16C62/62A/R62, always maintain these bits clear. 6: PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C62/62A/R62, always maintain these bits clear. 1997 Microchip Technology Inc. Bit 5 Bit 4 ...
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... Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: The IRP and RP1 bits are reserved on the PIC16C63/R63, always maintain these bits clear. 5: PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C63/R63, always maintain these bits clear. 1997 Microchip Technology Inc. Bit 5 Bit 4 ...
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... Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: The IRP and RP1 bits are reserved on the PIC16C63/R63, always maintain these bits clear. 5: PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C63/R63, always maintain these bits clear. 1997 Microchip Technology Inc. Bit 5 Bit 4 ...
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... T2CKPS1 T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu SSPM1 SSPM0 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M1 CCP1M0 --00 0000 --00 0000 — — 1997 Microchip Technology Inc. ...
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... The BOR bit is reserved on the PIC16C64, always maintain this bit set. 5: The IRP and RP1 bits are reserved on the PIC16C64/64A/R64, always maintain these bits clear. 6: PIE1<6> and PIR1<6> are reserved on the PIC16C64/64A/R64, always maintain these bits clear. 1997 Microchip Technology Inc. Bit 5 Bit 4 ...
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... CCP1M1 CCP1M0 --00 0000 --00 0000 OERR RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M1 CCP2M0 --00 0000 --00 0000 — — 1997 Microchip Technology Inc. ...
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... The BOR bit is reserved on the PIC16C65, always maintain this bit set. 5: The IRP and RP1 bits are reserved on the PIC16C65/65A/R65, always maintain these bits clear. 6: PIE1<6> and PIR1<6> are reserved on the PIC16C65/65A/R65, always maintain these bits clear. 1997 Microchip Technology Inc. Bit 5 Bit 4 ...
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... CCP1M1 CCP1M0 --00 0000 --00 0000 OERR RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M1 CCP2M0 --00 0000 --00 0000 — — 1997 Microchip Technology Inc. ...
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... PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear. 5: PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'. 6: PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear. 1997 Microchip Technology Inc. Bit 5 Bit 4 ...
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... DC C 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu — — 1111 1111 1111 1111 — — — — — — ---0 0000 ---0 0000 INTF RBIF 0000 000x 0000 000u — — 1997 Microchip Technology Inc. ...
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... Note: a subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. 1997 Microchip Technology Inc recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the bits from the STATUS register ...
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... DS30234D-page 36 Note: To achieve a 1:1 prescaler assignment for TMR0 register, assign the prescaler to the Watchdog Timer. R/W-1 R/W-1 R/W-1 R/W-1 PSA PS2 PS1 PS0 128 R = Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ Value at POR reset 1997 Microchip Technology Inc. ...
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... Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 1997 Microchip Technology Inc. Note: Interrupt flag bits get set when an interrupt ...
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... Disables the TMR1 overflow interrupt DS30234D-page 38 Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. R/W-0 R/W-0 R/W-0 R/W-0 SSPIE CCP1IE TMR2IE TMR1IE bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1997 Microchip Technology Inc. ...
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... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt 1997 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 SSPIE ...
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... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS30234D-page 40 R/W-0 R/W-0 R/W-0 R/W-0 SSPIE CCP1IE TMR2IE TMR1IE bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1997 Microchip Technology Inc. ...
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... Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 1997 Microchip Technology Inc. Note: Interrupt flag bits get set when an interrupt ...
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... GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS30234D-page 42 R/W-0 R/W-0 R/W-0 R/W-0 SSPIF CCP1IF TMR2IF TMR1IF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1997 Microchip Technology Inc. ...
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... Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 1997 Microchip Technology Inc. R/W-0 R/W-0 ...
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... GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS30234D-page 44 R/W-0 R/W-0 R/W-0 R/W-0 SSPIF CCP1IF TMR2IF TMR1IF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1997 Microchip Technology Inc. ...
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... U-0 — — — — bit7 bit 7-1: Unimplemented: Read as '0' bit 0: CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt 1997 Microchip Technology Inc. U-0 U-0 U-0 R/W-0 — — — CCP2IE bit0 PIC16C6X R = Readable bit ...
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... GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. U-0 U-0 U-0 R/W-0 — — — CCP2IF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1997 Microchip Technology Inc. ...
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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0: BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) 1997 Microchip Technology Inc. Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent resets to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a “ ...
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... Note: PIC16C6X devices with 4K or less of pro- GOTO, CALL gram PCLATH<4>. The use of PCLATH<4> Opcode <10:0> general purpose read/write bit is not rec- ommended since this may affect upward compatibility with future products. memory ignore paging bit 1997 Microchip Technology Inc. ...
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... Data Memory 7Fh Bank 0 For memory map detail see Figure 4-5, Figure 4-6, Figure 4-7, and Figure 4-8. 1997 Microchip Technology Inc. 4.5 Indirect Addressing, INDF and FSR Registers Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The INDF register is not a physical register ...
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... PIC16C6X NOTES: DS30234D-page 50 1997 Microchip Technology Inc. ...
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... STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6> are always ; read as '0'. 1997 Microchip Technology Inc. PIC16C6X FIGURE 5-1: BLOCK DIAGRAM OF THE RA3:RA0 PINS AND THE RA5 PIN Data bus Port Q ...
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... Input/output or external clock input for Timer0. Output is open drain type. Input/output or slave select input for synchronous serial port. Bit 4 Bit 3 Bit 2 Bit 1 (1) RA4 RA3 RA2 RA1 (1) Value on: Value on all Bit 0 POR, other resets BOR RA0 --xx xxxx --uu uuuu --11 1111 --11 1111 1997 Microchip Technology Inc. ...
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... PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB port change interrupt with flag bit RBIF (INTCON<0>). 1997 Microchip Technology Inc. PIC16C6X This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the inter- ...
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... TRIS Latch D Q TTL Input CK Buffer RD TRIS Port EN RD Port Schmitt Trigger Buffer and Value on: Value on all Bit 0 POR, other resets BOR RB0 xxxx xxxx uuuu uuuuu 1111 1111 1111 1111 PS0 1111 1111 1111 1111 1997 Microchip Technology Inc. ...
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... ST RC2/CCP1 bit2 ST RC3/SCK/SCL bit3 ST RC4/SDI/SDA bit4 ST RC5/SDO bit5 ST RC6 bit6 ST RC7 bit7 ST Legend Schmitt Trigger input 1997 Microchip Technology Inc. FIGURE 5-6: PORT/PERIPHERAL Select Peripheral Data Out Data bus D WR PORT CK Data Latch D WR TRIS CK TRIS Latch RD TRIS Peripheral ( PORT ...
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... Input/output port pin or USART Asynchronous Receive, or USART Syn- chronous Data Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RC5 RC4 RC3 RC2 RC1 2 C modes mode modes mode). Value on: Value on all Bit 0 POR, other resets BOR RC0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 1997 Microchip Technology Inc. ...
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... RD6 88h TRISD PORTD Data Direction Register 89h TRISE IBF OBF Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by PORTD. 1997 Microchip Technology Inc. FIGURE 5-7: Data bus WR PORT WR TRIS RD PORT Note 1: I/O pins have protection diodes to V ...
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... RD PORT Note 1: I/O pins have protection diodes to V U-0 R/W-1 R/W-1 R/W-1 — bit2 bit1 bit0 bit0 Q (1) I/O pin Q Schmitt Trigger input buffer and Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1997 Microchip Technology Inc. ...
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... TRISE IBF OBF IBOV Legend unknown unchanged unimplemented locations read as '0'. Shaded cells not used by PORTE. 1997 Microchip Technology Inc. Function (1) Input/output port pin or Read control input in parallel slave port mode Not a read operation 0 = Read operation. The system reads the PORTD register (if ...
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... Therefore, at higher clock frequencies, NOP a write followed by a read may be prob- MOVF PORTB,W lematic. PORTB<3:0> Outputs PORT latch PORT pins ---------- --------- ; 01pp pppp 11pp pppp ; 10pp pppp 11pp pppp ; ; 10pp pppp 11pp pppp ; 10pp pppp 10pp pppp - instruction cycle propagation delay PD 1997 Microchip Technology Inc. ...
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... An interrupt is generated and latched into flag bit PSPIF when a read or write operation is completed. PSPIF must be cleared by the user in firmware and the interrupt can be disabled by clearing the interrupt enable bit PSPIE (PIE1<7>). 1997 Microchip Technology Inc. PIC16C6X FIGURE 5-11: PORTD AND PORTE AS A PARALLEL SLAVE PORT Data bus ...
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... SSPIF CCP1IF TMR2IF TRM1IF (2) (2) TXIE SSPIE CCP1IE TMR2IE TMR1IE Value on: Value on all Bit 0 POR, other resets BOR PSP0 xxxx xxxx uuuu uuuu RE0 ---- -xxx ---- -uuu 0000 -111 0000 -111 0000 0000 0000 0000 0000 0000 0000 0000 1997 Microchip Technology Inc. ...
Page 63
... TMR1 can be used in conjunction with the Capture/ Compare/PWM module. When used with a CCP mod- ule, Timer1 is the time-base for 16-bit capture or 16-bit compare and must be synchronized to the device. 1997 Microchip Technology Inc. PIC16C6X 6.3 Timer2 Overview Applicable Devices ...
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... PIC16C6X NOTES: DS30234D-page 64 1997 Microchip Technology Inc. ...
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... T0 T0+1 TMR0 Instruction Executed 1997 Microchip Technology Inc. (OPTION<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are dis- cussed in detail in Section 7.2. The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The pres- caler assignment is controlled in software by control bit PSA (OPTION< ...
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... NT0 reads NT0 FFh 00h Inst (PC+1) Dummy cycle Inst (PC) PC+4 PC+5 PC+6 MOVF TMR0,W NT0+1 T0 Read TMR0 Read TMR0 reads NT0 reads NT0 + 01h 02h 0004h 0005h Inst (0004h) Inst (0005h) Dummy cycle Inst (0004h) 1997 Microchip Technology Inc. ...
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... Therefore, the error in measuring the interval between two edges on Timer0 input = 4Tosc max. 2: External clock if no prescaler selected, prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. 1997 Microchip Technology Inc. When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type pres- caler so that the prescaler output is symmetrical ...
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... Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment SYNC Cycles PSA 8-bit Prescaler 1MUX PS2:PS0 PSA WDT Time-out TMR0, Data Bus 8 TMR0 reg Set flag bit T0IF on Overflow 1997 Microchip Technology Inc. ...
Page 69
... TRISA — — Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by Timer0. Note 1: TRISA<5> and bit PEIE are not implemented on the PIC16C61, read as '0'. 1997 Microchip Technology Inc. BSF STATUS, RP0 ;Bank 1 MOVLW b'xx0x0xxx' ;Select clock source and prescale value of ...
Page 70
... PIC16C6X NOTES: DS30234D-page 70 1997 Microchip Technology Inc. ...
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... Internal clock (Fosc/4) bit 0: TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 1997 Microchip Technology Inc. Timer1 also has an internal “reset input”. This reset can be generated by CCP1 or CCP2 (Capture/Compare/ PWM) module. See Section 10.0 for details. Figure 8-1 shows the Timer1 control register. ...
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... Refer to applicable electrical specification sec- tion, parameters 40, 42, 45, 46, and 47. 0 TMR1L 1 TMR1ON T1SYNC on/off (3) 1 Prescaler T1OSCEN Fosc/4 Enable Internal 0 (1) Oscillator Clock TMR1CS T1CKPS1:T1CKPS0 Synchronized clock input Synchronize det 2 SLEEP input 1997 Microchip Technology Inc. ...
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... This may produce an unpre- dictable value in the timer register. Reading the 16-bit value requires some care. Example 8 example routine to read the 16-bit timer value. This is useful if the timer cannot be stopped. 1997 Microchip Technology Inc. PIC16C6X EXAMPLE 8-1: READING A 16-BIT FREE-RUNNING TIMER ; ...
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... CCP1IF TMR2IF (1) (1) CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 TXIE SSPIE Value on: Value on Bit 0 POR, all other BOR resets 0000 000x 0000 000u RBIF TMR1IF 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1997 Microchip Technology Inc. ...
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... T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = 1:1 prescale 01 = 1:4 prescale 1x = 1:16 prescale 1997 Microchip Technology Inc. 9.1 Timer2 Prescaler and Postscaler Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The prescaler and postscaler counters are cleared when any of the following occurs: • ...
Page 76
... SSPIE CCP1IE TMR2IE Value on: Value on Bit 1 Bit 0 POR, all other BOR resets INTF RBIF 0000 000x 0000 000u TMR2IF TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1997 Microchip Technology Inc. ...
Page 77
... The PWMs will have the same frequency, and update rate (TMR2 interrupt). PWM Capture None PWM Compare None 1997 Microchip Technology Inc. PIC16C6X CCP2 module: Capture/Compare/PWM Register2 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. All are readable and writable. ...
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... CCP1IF following any such change in operating mode Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ =Value at POR reset OPERATION BLOCK DIAGRAM Set CCP1IF PIR1<2> CCPR1H CCPR1L Capture Enable TMR1H TMR1L CCP1CON<3:0> 1997 Microchip Technology Inc. ...
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... RC2/CCP1 R TRISC<2> Output Enable CCP1CON<3:0> Mode Select 1997 Microchip Technology Inc. 10.2.1 CCP PIN CONFIGURATION The user must configure the RC2/CCP1 pin as an out- put by clearing the TRISC<2> bit. Note: Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level ...
Page 80
... Maximum PWM resolution (bits) for a given PWM frequency: Note: If the PWM duty cycle value is longer than the PWM period the CCP1 pin will not be forced to the low level. • OSC (TMR2 prescale value) Tosc • (TMR2 prescale value OSC log F PWM = bits log(2) 1997 Microchip Technology Inc. ...
Page 81
... The PIR1<6> and PIE1<6> bits are reserved, always maintain these bits clear. 4: These registers are associated with the CCP2 module, which is only implemented on the PIC16C63/R63/65/65A/R65/66/67. 1997 Microchip Technology Inc. In order to achieve higher resolution, the PWM fre- quency must be decreased. In order to achieve higher PWM frequency, the resolution must be decreased ...
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... TMR2IE TMR1IE 0000 0000 0000 0000 — CCP2IE ---- ---0 ---- ---0 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1997 Microchip Technology Inc. ...
Page 83
... SPI modules is the same regardless of the device: 11.2 SPI Mode for PIC16C62/62A/R62/63/R63/64/ 64A/R64/65/65A/R65 .......................................84 11.3 SPI Mode for PIC16C66/67..............................89 11.4 I2C™ Overview ................................................95 11.5 SSP I2C Operation...........................................99 Refer to Application Note AN578, “Use of the SSP Mod- 2 ule in the I C Multi-Master Environment.” 1997 Microchip Technology Inc. PIC16C6X DS30234D-page 83 ...
Page 84
... Receive not complete, SSPBUF is empty 2 Transmit (I C mode only Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty DS30234D-page 84 R-0 R-0 R-0 R mode only mode only Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ =Value at POR reset 1997 Microchip Technology Inc. ...
Page 85
... C firmware controlled Master Mode (slave idle) 2 1110 = I C slave mode, 7-bit address with start and stop bit interrupts enabled 2 1111 = I C slave mode, 10-bit address with start and stop bit interrupts enabled 1997 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 SSPM3 SSPM2 ...
Page 86
... FIGURE 11-3: SSP BLOCK DIAGRAM (SPI MODE) Read SSPBUF reg SSPSR reg RC4/SDI/SDA bit0 RC5/SDO SS Control Enable RA5/SS Edge Select 2 Clock Select SSPM3:SSPM0 4 Edge Select RC3/SCK/ SCL TRISC<3> 1997 Microchip Technology Inc. Internal data bus Write shift clock TMR2 output 2 T Prescaler CY 4, 16, 64 ...
Page 87
... Shift Register (SSPSR) MSb PROCESSOR 1 1997 Microchip Technology Inc. The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor broadcast data by the software protocol. In master mode the data is transmitted/received as soon as the SSPBUF register is written to ...
Page 88
... Value on: Value on Bit 0 POR, all other BOR Resets RBIF 0000 000x 0000 000u xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 --11 1111 --11 1111 1111 1111 1111 1111 UA BF --00 0000 --00 0000 1997 Microchip Technology Inc. ...
Page 89
... BF: Buffer Full Status bit 2 Receive (SPI and I C modes Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty 2 Transmit (I C mode only Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty 1997 Microchip Technology Inc. R-0 R-0 R-0 R mode only) ...
Page 90
... I C slave mode, 10-bit address with start and stop bit interrupts enabled DS30234D-page 90 R/W-0 R/W-0 R/W-0 R/W-0 SSPM3 SSPM2 SSPM1 SSPM0 bit0 /4 OSC /16 OSC /64 OSC R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ =Value at POR reset 1997 Microchip Technology Inc. ...
Page 91
... Example 11-2 shows the loading of the SSPBUF (SSPSR) for data transmission. The shaded instruction is only required if the received data is meaningful. 1997 Microchip Technology Inc. EXAMPLE 11-2: LOADING THE SSPBUF (SSPSR) REGISTER (PIC16C66/67) BCF ...
Page 92
... In sleep mode, the slave can transmit and receive data and wake the device from sleep. SPI Slave SSPM3:SSPM0 = 010xb SDO SDI SDI SDO LSb Serial Clock SCK SCK ) Serial Input Buffer (SSPBUF) Shift Register (SSPSR) MSb LSb PROCESSOR 2 1997 Microchip Technology Inc. ...
Page 93
... SS (optional) SCK (CKP = 0) SCK (CKP = 1) bit7 SDO SDI (SMP = 0) bit7 SSPIF 1997 Microchip Technology Inc. Note: When the SPI is in Slave Mode with SS pin control enabled, (SSPCON<3:0> = 0100) the SPI module will reset if the SS pin is set Note: If the SPI is used in Slave Mode with CKE = '1', then the SS pin control must be enabled ...
Page 94
... SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 PORTA Data Direction register D R/W UA bit1 bit0 bit0 Value on Value on all Bit 0 Power-on other resets Reset RBIF 0000 000x 0000 000u xxxx xxxx uuuu uuuu --11 1111 --11 1111 1111 1111 1111 1111 BF 0000 0000 0000 0000 1997 Microchip Technology Inc. ...
Page 95
... Procedure that ensures that only one of the master devices will control the bus. This ensure that the transfer data does not get corrupted. Synchronization Procedure where the clock signals of two or more devices are synchronized. 1997 Microchip Technology Inc. PIC16C6X In both cases the master generates the clock signal. The output stages of the clock (SCL) and data (SDA) lines must have an open-drain or open-collector in order to perform the wired-AND function of the bus ...
Page 96
... R/W ACK Wait Data State ACKNOWLEDGE not acknowledge acknowledge Clock Pulse for Acknowledgment acknowledgment signal from receiver Stop ACK Condition 1997 Microchip Technology Inc. ...
Page 97
... From master to slave S = Start Condition From slave to master P = Stop Condition 1997 Microchip Technology Inc. SCL is high), but occurs after a data transfer acknowl- edge pulse (not the bus-free state). This allows a mas- ter to send “commands” to the slave and then receive the requested information or to address a different slave device ...
Page 98
... The first device to complete its high period will pull the SCL line low. The SCL line high time is deter- mined by the device with the shortest high period, Figure 11-23. FIGURE 11-23: CLOCK SYNCHRONIZATION start counting wait state HIGH period CLK 1 counter CLK reset 2 SCL 1997 Microchip Technology Inc. ...
Page 99
... SSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer (SSPBUF) • SSP Shift Register (SSPSR) - Not directly acces- sible • SSP Address Register (SSPADD) 1997 Microchip Technology Inc. The SSPCON register allows control of the I tion. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2 • ...
Page 100
... Receive first (high) byte of Address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Generate ACK SSPBUF Pulse Yes Yes Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes 1997 Microchip Technology Inc. ...
Page 101
... R/W=0 SDA SCL S SSPIF (PIR1<3>) BF (SSPSTAT<0>) SSPOV (SSPCON<6>) 1997 Microchip Technology Inc. An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft- ware. The SSPSTAT register is used to determine the status of the byte. Receiving Data ACK ACK ...
Page 102
... A2 A1 ACK SCL held low while CPU responds to SSPIF cleared in software SSPBUF is written in software Set bit after writing to SSPBUF (the SSPBUF must be written-to before the CKP bit can be set) Transmitting Data ACK From SSP interrupt service routine 1997 Microchip Technology Inc. ...
Page 103
... PIR1<6> and PIE1<6> are reserved, always maintain these bits clear. 3: The SMP and CKE bits are implemented on the PIC16C66/67 only. All other PIC16C6X devices have these two bits unim- plemented, read as '0'. 1997 Microchip Technology Inc. 11.5.3 MULTI-MASTER MODE In multi-master mode, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free ...
Page 104
... PRIOR_ADDR_MATCH = FALSE; } DS30234D-page 104 2 C MODULE IN IDLE_MODE, RCV_MODE OR XMIT_MODE Set interrupt Send ACK = 0; set XMIT_MODE; } else if (R set RCV_MODE; End of transmission; Go back to IDLE_MODE; { PRIOR_ADDR_MATCH = TRUE; Send ACK = 0; while (SSPADD not updated) Hold SCL low; Clear Set RCV_MODE; } 1997 Microchip Technology Inc. ...
Page 105
... TSR empty 0 = TSR full bit 0: TX9D: 9th bit of transmit data. Can be parity bit. 1997 Microchip Technology Inc. minals and personal computers can be configured as a half duplex synchronous system that can commu- nicate with peripheral devices such as A/D or D/A inte- grated circuits, Serial EEPROMs etc. ...
Page 106
... Overrun error (Can be cleared by clearing bit CREN overrun error bit 0: RX9D: 9th bit of received data (Can be parity bit) DS30234D-page 106 U-0 R-0 R-0 R-x — FERR OERR RX9D bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset x = unknown 1997 Microchip Technology Inc. ...
Page 107
... TX9 18h RCSTA SPEN RX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented read as '0'. Shaded cells are not used by the BRG. 1997 Microchip Technology Inc. EXAMPLE 12-1: CALCULATING BAUD Desired Baud rate = Fosc / ( 1)) 9600 = X = Calculated Baud Rate=16000000 / (64 (25 + 1)) = 9615 ...
Page 108
... MHz SPBRG % value KBAUD ERROR (decimal 1.203 +0.23 92 2.380 -0.83 46 9.322 -2.90 11 18.64 -2. 111 0.437 - 255 32.768 kHz SPBRG SPBRG % value % value ERROR (decimal) KBAUD ERROR (decimal) +0.16 51 0.256 -14.67 +0. -6. 0.512 - - 255 0.0020 - 255 1997 Microchip Technology Inc 255 ...
Page 109
... For the PIC16C63/R63/65/65A/R65 the asynchronous high speed mode (BRGH = 1) may experience a high rate of receive errors recommended that BRGH = 0. If you desire a higher baud rate than BRGH = 0 can support, refer to the device errata for additional information or use the PIC16C66/67. 1997 Microchip Technology Inc. 10 MHz SPBRG ...
Page 110
... Baud CLK for all but start bit Samples bit0 Start Bit First falling edge after RX pin goes low Second rising edge Samples Samples Start Bit Baud clk for all but start bit Second rising edge 1 2 Samples Bit0 bit1 Samples bit0 3 4 1997 Microchip Technology Inc. ...
Page 111
... FIGURE 12-6: RX PIN SAMPLING SCHEME (BRGH = (PIC16C66/67) RX (RC7/RX/DT pin) baud CLK x16 CLK 1997 Microchip Technology Inc. Start bit Baud CLK for all but start bit Samples PIC16C6X Bit0 DS30234D-page 111 ...
Page 112
... TSR register (if the TSR is empty). In such a case, an incorrect ninth data bit maybe loaded in the TSR regis- ter. Data Bus TXREG register 8 LSb Pin Buffer 0 and Control TSR register TRMT TX9 TX9D RC6/TX/CK pin SPEN 1997 Microchip Technology Inc. ...
Page 113
... Legend unknown unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. Note 1: PSPIF and PSPIE are reserved on the PIC16C63/R63/66, always maintain these bits clear. 2: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear. 1997 Microchip Technology Inc. 5. Enable the transmission by setting bit TXEN, which will also set bit TXIF ...
Page 114
... RSR register MSb Stop (8) Data RX9 Recovery RX9D RCIF Interrupt RCIE Start Stop bit7/8 Stop bit bit0 bit7/8 bit bit WORD 2 WORD 1 RCREG RCREG FERR LSb 0 1 Start RCREG register FIFO 8 Data Bus Start bit Stop bit7/8 bit 1997 Microchip Technology Inc. ...
Page 115
... Legend unknown unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception. Note 1: PSPIE and PSPIF are reserved on the PIC16C63/R63/66, always maintain these bits clear. 2: PIE1<6> and PIR1<6> are reserved, always maintain these bits clear. 1997 Microchip Technology Inc. 6. Flag bit RCIF will be set when reception is com- plete, and an interrupt will be generated if enable bit RCIE was set ...
Page 116
... If interrupts are desired, then set enable bit TXIE 9-bit transmission is desired, then set bit TX9. 5. Enable the transmission by setting enable bit TXEN 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register. 1997 Microchip Technology Inc. ...
Page 117
... Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words FIGURE 12-13: SYNCHRONOUS TRANSMISSION THROUGH TXEN RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit 1997 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RCIF TXIF SSPIF ...
Page 118
... TRMT Value on Value on Bit 0 POR, all other BOR Resets TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 1997 Microchip Technology Inc. ...
Page 119
... RC6/TX/CK pin Write to bit SREN SREN bit '0' CREN bit RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRG = '0'. 1997 Microchip Technology Inc Q4Q1 Q4Q1 Q4Q1 bit1 bit2 bit3 bit4 bit5 PIC16C6X bit6 bit7 ...
Page 120
... RCIE was set. 6. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. Read the 8-bit received data by reading the RCREG register any error occurred, clear the error by clearing enable bit CREN. 1997 Microchip Technology Inc. ...
Page 121
... Legend unknown unimplemented locations read as '0'. Shaded cells are not used for Synchronous Slave Reception. Note 1: PSPIF and PSPIE are reserved on the PIC16C63/R63/66, always maintain these bits clear. 2: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear. 1997 Microchip Technology Inc. Bit 5 Bit 4 ...
Page 122
... PIC16C6X NOTES: DS30234D-page 122 1997 Microchip Technology Inc. ...
Page 123
... FOSC1:FOSC0: Oscillator Selection bits oscillator oscillator oscillator oscillator 1997 Microchip Technology Inc. timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which pro- vides a fi ...
Page 124
... All of the CP1:CP0 pairs have to be given the same value to implement the code protection scheme listed. DS30234D-page 124 — — CP1 CP0 PWRTE WDTE FOSC1 FOSC0 — BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 (2) (1) (1) Register: CONFIG Address 2007h bit0 Register: CONFIG Address 2007h bit0 1997 Microchip Technology Inc. ...
Page 125
... Use of a series cut crystal may give a frequency out of the crystal manufacturers specifica- tions. When in LP, XT modes, the device can have an external clock source to drive the OSC1/CLKIN pin (Figure 13-5). 1997 Microchip Technology Inc. PIC16C6X FIGURE 13-4: CRYSTAL/CERAMIC RESONATOR OPERATION (HS OSC ...
Page 126
... FOR CRYSTAL OSCILLATOR FOR PIC16C61 OSC1 OSC2 100 100 CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR FOR PIC16C62/62A/R62/63/ R63/64/64A/R64/65/65A/R65/ 66/67 Cap. Cap. Range Range Freq 47-68 pF 47- 15-33 pF 15-33 pF 15-33 pF 15-33 pF Crystals Used 20 PPM 20 PPM 50 PPM 50 PPM 30 PPM 30 PPM 1997 Microchip Technology Inc. ...
Page 127
... Devices 74AS04 74AS04 74AS04 0.1 F XTAL 1997 Microchip Technology Inc. 13.2.4 RC OSCILLATOR For timing insensitive applications the RC device option offers additional cost savings. The RC oscillator fre- quency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature ...
Page 128
... MCLR reset path has a noise filter to detect and ignore small pulses. See parameter #34 for pulse width specifications. It should be noted that a WDT Reset does not drive the MCLR pin low. Enable PWRT (3) Enable OST 1997 Microchip Technology Inc. S Chip Reset R Q ...
Page 129
... V DD Internal Reset V DD Internal Reset 1997 Microchip Technology Inc. The power-up time delay will vary from chip to chip due temperature, and process variation. See DC DD parameters for details. 13.4.3 OSCILLATOR START-UP TIMER (OST) The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over ...
Page 130
... Illegal set on a Power-on Reset WDT Reset WDT Wake-up MCLR reset during normal operation MCLR reset during SLEEP or interrupt wake-up from SLEEP Wake-up from SLEEP 1024 T OSC — Wake up from Brown-out SLEEP 1024 T OSC OSC 72 ms — 1997 Microchip Technology Inc. ...
Page 131
... Interrupt wake-up from SLEEP Legend unchanged unknown unimplemented bit read as '0'. Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC+1. 1997 Microchip Technology Inc. PD Power-on Reset 1 ...
Page 132
... Microchip Technology Inc. ...
Page 133
... When the wake-up is due to an interrupt and the global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h) after execution See Table 13-10 and Table 13-11 for reset value for specific conditions. 1997 Microchip Technology Inc. Power-on Reset Brown-out ...
Page 134
... MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 13-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS30234D-page 134 T PWRT T OST T PWRT T OST ) DD T PWRT T OST 1997 Microchip Technology Inc. ): CASE CASE 2 DD ...
Page 135
... R1 = 100 will limit any current flowing into MCLR from external capacitor C in the event of MCLR/V PP down due to Electrostatic Discharge (ESD) or Electrostatic Overstress (EOS). 1997 Microchip Technology Inc. FIGURE 13-15: EXTERNAL BROWN-OUT V DD 33k Note 1: This circuit will activate reset when V goes below (Vz + 0.7V) where Vz = Zener voltage ...
Page 136
... Perform the following to ensure that interrupts are globally disabled. LOOP BCF INTCON,GIE BTFSC INTCON,GIE GOTO LOOP : (Figure 13- ;Disable Global ;Interrupt bit ;Global Interrupt ;Disabled? ;NO, try again ;Yes, continue ;with program flow 1997 Microchip Technology Inc. ...
Page 137
... Yes PIC16C64 Yes Yes PIC16C65 Yes Yes PIC16C65A Yes Yes PIC16CR65 Yes Yes PIC16C66 Yes Yes PIC16C67 Yes Yes 1997 Microchip Technology Inc. Wake-up (If in SLEEP mode) Interrupt to CPU T0IF T0IE INTF INTE RBIF RBIE PEIE GIE Yes - - - Yes Yes Yes ...
Page 138
... RBIF may not get set Interrupt Latency (2) PC+1 PC+1 Inst (PC+1) — Dummy Cycle Inst (PC) for asynchronous interrupt. CY 00h) in the TMR0 register will set 0004h 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) 1997 Microchip Technology Inc. ...
Page 139
... MOVWF STATUS SWAPF W_TEMP,F SWAPF W_TEMP,W 1997 Microchip Technology Inc. defined in all banks and must be defined at the same offset from the bank base address (i.e., if W_TEMP is defined at 0x20 in bank 0, it must also be defined at 0xA0 in bank 1, 0x120 in bank 2, and 0x1A0 in bank 3). ...
Page 140
... PSA 0 1 MUX WDT Time-out Bit 6 Bit 5 Bit 4 Bit 3 (1) CP1 CP0 BODEN PWRTE INTEDG T0CS T0SE PSA = Min., Temperature = Max., max. PS2:PS0 To TMR0 (Figure 7-6) PSA Bit 2 Bit 1 Bit 0 (1) WDTE FOSC1 FOSC0 PS2 PS1 PS0 1997 Microchip Technology Inc. ...
Page 141
... CCP capture mode interrupt. 5. Parallel Slave Port read or write. 6. USART (synchronous slave mode). 1997 Microchip Technology Inc. Other peripherals can not generate interrupts since during SLEEP, no on-chip Q clocks are present. When the SLEEP instruction is being executed, the next instruction ( pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled) ...
Page 142
... Specifications (Literature #DS30228). FIGURE 13-23: TYPICAL IN-CIRCUIT SERIAL External Connector Signals + CLK Data I 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h (see programming specifica- IHH PROGRAMMING CONNECTION To Normal Connections PIC16CXX MCLR/V PP RB6 RB7 Normal Connections 1997 Microchip Technology Inc. ...
Page 143
... Assigned to < > Register bit field In the set of i talics User defined term (font is courier) 1997 Microchip Technology Inc. PIC16C6X The instruction set is highly orthogonal and is grouped into three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations ...
Page 144
... TO 00 0000 0110 0011 1 C,DC,Z 11 110x kkkk kkkk 1010 kkkk kkkk 1997 Microchip Technology Inc. Notes 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 ...
Page 145
... Q Cycle Activity Decode Read register 'f' Example ADDWF FSR, 0 Before Instruction W = 0x17 FSR = 0xC2 After Instruction W = 0xD9 FSR = 0xC2 1997 Microchip Technology Inc. ANDLW Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: . Words: Cycles: Q Cycle Activity Process Write to data W Example ANDWF ...
Page 146
... Q3 Q4 Decode Read Process No- register 'f' data Operation (2nd Cycle No- No- No- No- Operation Operation Operation Operation HERE BTFSC FLAG,1 FALSE GOTO PROCESS_CODE • TRUE • • Before Instruction PC = address HERE After Instruction if FLAG<1> address TRUE if FLAG<1>= address FALSE 1997 Microchip Technology Inc. ...
Page 147
... Operation Operation Example HERE BTFSC FALSE GOTO • TRUE • • Before Instruction PC = address HERE After Instruction if FLAG<1> FLAG<1> 1997 Microchip Technology Inc. CALL Syntax: Operands: Operation: Status Affected: bfff ffff Encoding: Description: instruction. CY Words Cycles: Process No- Q Cycle Activity: data ...
Page 148
... CLRWDT instruction resets the Watch- dog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set Decode No- Process Clear Operation data WDT Counter CLRWDT Before Instruction WDT counter = ? After Instruction WDT counter = 0x00 WDT prescaler 1997 Microchip Technology Inc. ...
Page 149
... Cycles Cycle Activity Decode Read register 'f' Example DECF CNT, 1 Before Instruction CNT = Z = After Instruction CNT = Z = 1997 Microchip Technology Inc. DECFSZ Syntax: Operands: Operation: Status Affected: dfff ffff Encoding: Description Words: Process Write to data destination Cycles: Q Cycle Activity: 0x13 If Skip: 0x13 0xEC ...
Page 150
... Z 00 1010 dfff ffff The contents of register 'f' are incre- mented the result is placed in the W register the result is placed back in register 'f Decode Read Process Write to register data destination 'f' INCF CNT, 1 Before Instruction CNT = 0xFF After Instruction CNT = 0x00 1997 Microchip Technology Inc. ...
Page 151
... Before Instruction PC = address HERE After Instruction CNT = CNT + 1 if CNT address CONTINUE if CNT address HERE +1 1997 Microchip Technology Inc. IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: dfff ffff Words: Cycles: Q Cycle Activity: CY Example Q3 Q4 Process Write to data destination ...
Page 152
... After Instruction W = 0x5A Move label ] MOVWF 127 (W) (f) None 00 0000 1fff ffff Move data from W register to register . ' Decode Read Process Write register data register 'f' 'f' MOVWF OPTION_REG Before Instruction OPTION = 0xFF W = 0x4F After Instruction OPTION = 0x4F W = 0x4F 1997 Microchip Technology Inc. ...
Page 153
... PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it. Words: 1 Cycles: 1 Example To maintain upward compatibility with future PIC16CXX products, do not use this instruction. 1997 Microchip Technology Inc. RETFIE Syntax: Operands: Operation: Status Affected: 0xx0 0000 Encoding: Description ...
Page 154
... Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction Decode No- No- Pop from Operation Operation the Stack No- No- No- No- Operation Operation Operation Operation RETURN After Interrupt PC = TOS 1997 Microchip Technology Inc. ...
Page 155
... Words: 1 Cycles Cycle Activity Decode Read register 'f' Example RLF REG1,0 Before Instruction REG1 C After Instruction REG1 W C 1997 Microchip Technology Inc. RRF Syntax: Operands: Operation: Status Affected: Encoding: dfff ffff Description: Words: Cycles Cycle Activity: Process Write to data destination Example = 1110 0110 ...
Page 156
... The result is placed in the W register Decode Read Process Write to W literal 'k' data SUBLW 0x02 Before Instruction After Instruction result is positive Before Instruction After Instruction result is zero Before Instruction After Instruction W = 0xFF result is negative 1997 Microchip Technology Inc. ...
Page 157
... Before Instruction REG1 = After Instruction REG1 = 0xFF result is negative 1997 Microchip Technology Inc. SWAPF Syntax: Operands: Operation: Status Affected: dfff ffff Encoding: Description: Words: Cycles Cycle Activity: Process Write to data destination Example TRIS Syntax: Operands: Operation: Status Affected: None Encoding: Description: ...
Page 158
... Exclusive OR the contents of the W register with register 'f the result is stored in the W register the result is stored back in register 'f Decode Read Process Write to register data destination 'f' XORWF REG 1 Before Instruction REG = 0xAF W = 0xB5 After Instruction REG = 0x1A W = 0xB5 1997 Microchip Technology Inc. ...
Page 159
... Microsoft Windows 3.x environment were chosen to best make these fea- tures available to you, the end user compliant version of PICMASTER is available for European Union (EU) countries. 1997 Microchip Technology Inc. 15.3 ICEPIC: Low-cost PIC16CXXX In-Circuit Emulator ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers ...
Page 160
... MPASM offers full featured Macro capabilities, condi- tional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. MPASM allows full symbolic debugging from PICMASTER, Microchip’s Universal Emulator System. 1997 Microchip Technology Inc. ...
Page 161
... TECH-MP, edition for imple- menting more complex systems. Both versions include Microchip’s fuzzy LAB stration board for hands-on experience with fuzzy logic systems implementation. 1997 Microchip Technology Inc. 15.14 MP-DriveWay Generator MP-DriveWay is an easy-to-use Windows-based Appli- cation Code Generator. With MP-DriveWay you can visually confi ...
Page 162
... PIC16C6X TABLE 15-1: DEVELOPMENT TOOLS FROM MICROCHIP Products Emulator DS30234D-page 162 Tools Software Programmers Boards Demo 1997 Microchip Technology Inc. ...
Page 163
... Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications recommended that the user select the device type that ensures the specifications required. 1997 Microchip Technology Inc. (except V , MCLR, and RA4) ..........................................-0. (Note 2) ...
Page 164
... Rext in kOhm. +125˚C for extended, +85˚C for industrial and +70˚C for commercial Conditions = 4 MHz 5.5V (Note MHz 5. 4.0V, WDT enabled 4.0V, WDT disabled + 4.0V, WDT disabled 4.0V, WDT disabled, - +125 and 1997 Microchip Technology Inc. ...
Page 165
... The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula 1997 Microchip Technology Inc. -40˚ 0˚C ...
Page 166
... DD 4.5V V 5.5V DD Note1 4.5V V 5.5V DD For entire V range DD For entire V range DD Note1 = 5V PIN Pin at hi- PIN DD impedance V V PIN XT, HS and PIN DD LP osc configuration I = 8.5 mA 4. 7.0 mA 4.5V - +125 1.6 mA 4. 1.2 mA 4.5V - +125 C 1997 Microchip Technology Inc. ...
Page 167
... The leakage current on the MCLR/V levels represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 3: Negative current is defined as current sourced by the pin. 1997 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C -40˚C 0˚ ...
Page 168
... C specifications only specifications only) T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z Hi-impedance High High Low Low SU Setup STO STOP condition Load condition Pin V SS for all pins except OSC2/CLKOUT for OSC2 output 1997 Microchip Technology Inc. ...
Page 169
... Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. 1997 Microchip Technology Inc ...
Page 170
... PIC16C61 — PIC16LC61 — OSC new value Typ† Max Units Conditions Note Note Note Note 1 — 0. Note 1 CY — — ns Note 1 — — ns Note 1 — 100 ns — — ns — — — — — — ns — — ns 1997 Microchip Technology Inc. ...
Page 171
... I/O Hi-impedance from MCLR Low 34 IOZ * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. PIC16C6X Min Typ† Max ...
Page 172
... Typ† Max Units Conditions No Prescaler 0. — CY With Prescaler 10 — No Prescaler 0. — CY With Prescaler 10 — No Prescaler — CY With Prescaler Greater of: — — ns Must also meet parameter 42 — ns — ns Must also meet parameter 42 — ns — prescale value (2, 4, ..., 256) — ns 1997 Microchip Technology Inc. ...
Page 173
... The percentage variation indicated here is part to part variation due to normal process distribution. The variation indi- cated is 3 standard deviation from average value for V 1997 Microchip Technology Inc. Note: The data presented in this section is a sta- tistical summary of data collected on units from different lots over a period of time and matrix samples ...
Page 174
... DD 0 3.3k 0 4.7k 0.4 0 10k 0.2 0 100k 5.5 6.0 0.0 3.0 FREQUENCY 10k Cext = 300 pF 100k 3.5 4.0 4.5 5.0 5.5 6.0 V (Volts VS. DD WATCHDOG TIMER DISABLED 25 C 3.5 4.0 4.5 5.0 5.5 6.0 V (Volts) DD 1997 Microchip Technology Inc. ...
Page 175
... Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-6: TYPICAL VS. WATCHDOG TIMER ENABLED 3.0 3.5 4.0 4.5 5.0 V (Volts) DD 1997 Microchip Technology Inc. FIGURE 17-7: MAXIMUM 3.0 3.5 5.5 6.0 PIC16C6X V PD VS. DD WATCHDOG DISABLED 125 - ...
Page 176
... C, the latter dominates explaining the apparently anomalous behavior. DS30234D-page 176 V FIGURE 17- -55 C 2.00 -40 C 1.80 1.60 1.40 125 C 1.20 1.00 0. 6.0 (INPUT THRESHOLD TH VOLTAGE) OF I/O PINS VS Max (- Typ Min (- 3.0 3.5 4.0 4.5 5.0 5.5 6.0 V (Volts) DD 1997 Microchip Technology Inc. ...
Page 177
... THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES VS. DD 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 3.0 3.5 4.0 1997 Microchip Technology Inc. V VS. 4.0 4.5 5.0 5.5 V (Volts) DD 4.5 5.0 5.5 V (Volts) DD PIC16C6X Max (- ...
Page 178
... FIGURE 17-13: MAXIMUM I DD VS. 10,000 1,000 100 10 10,000 100,000 DS30234D-page 178 1,000,000 Frequency (Hz) FREQUENCY (EXTERNAL CLOCK, -40 TO +85 C) 1,000,000 Frequency (Hz) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 100,000,000 10,000,000 6.0 5.5 5.0 4.5 4.0 3.5 3.0 100,000,000 10,000,000 1997 Microchip Technology Inc. ...
Page 179
... FIGURE 17-15: WDT TIMER TIME-OUT PERIOD V VS (Volts) DD 1997 Microchip Technology Inc. FREQUENCY (EXTERNAL CLOCK, -55 TO +125 C) 1,000,000 10,000,000 Frequency (Hz) FIGURE 17-16: TRANSCONDUCTANCE (gm) 9000 8000 7000 6000 5000 Max 4000 Max 3000 Typ 2000 Min 1000 Min. - PIC16C6X 6.0 5 ...
Page 180
... FIGURE 17-20 VS Max. -40 C -10 -15 -20 Min @ 85 C Typ -25 -30 -35 MIn -40 -45 -50 0.0 0 Max. -40 C 1.0 1.5 2.0 2.5 3.0 V (Volts VS Typ @ 25 C Max @ -40 C 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 V (Volts) OH 1997 Microchip Technology Inc. ...
Page 181
... V (Volts) OL TABLE 17-2: INPUT CAPACITANCE* Pin Name RA port RB port MCLR OSC1/CLKIN OSC2/CLKOUT T0CKI *All capacitance values are typical part to part variation of 25% (three standard deviations) should be taken into account. 1997 Microchip Technology Inc. FIGURE 17-22 Typ @ Min @ + 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2 ...
Page 182
... PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 NOTES: DS30234D-page 182 1997 Microchip Technology Inc. ...
Page 183
... Freq:200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications recommended that the user select the device type that ensures the specifications required. 1997 Microchip Technology Inc. (except V , MCLR, and RA4) ..........................................-0. ...
Page 184
... RAM data. measurements in active operation mode are: /2Rext (mA) with Rext in kOhm. +85˚C for industrial and +70˚C for commercial Conditions = 4 MHz 5.5V (Note MHz 5. 4.0V, WDT enabled 4.0V, WDT disabled + 4.0V, WDT disabled and 1997 Microchip Technology Inc. ...
Page 185
... For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Timer1 oscillator (when enabled) adds approximately the specification. This value is from charac- terization and is for design guidance only. This is not tested. 1997 Microchip Technology Inc. -40˚C T +85˚C for industrial and A 0˚ ...
Page 186
... DD V For entire V range DD For entire V range Note1 5V PIN SS A Vss Pin at hi- PIN DD impedance A Vss V V PIN DD A Vss XT, HS and PIN DD LP osc configuration 8.5 mA 4. 1.6 mA 4. -3.0 mA 4. -1.3 mA 4. RA4 pin 1997 Microchip Technology Inc. ...
Page 187
... PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/V els represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 1997 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C 0˚ ...
Page 188
... C specifications only specifications only) T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z Hi-impedance High High Low Low SU Setup STO STOP condition Load condition Pin Note 1: PORTD and PORTE are not imple mented on the PIC16C62. 1997 Microchip Technology Inc. ...
Page 189
... Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. 1997 Microchip Technology Inc ...
Page 190
... Max Units Conditions 75 200 ns Note 1 75 200 ns Note 1 35 100 ns Note 1 35 100 ns Note 1 — 0. Note 1 CY — — ns Note 1 — — ns Note 1 50 150 ns — — ns — — ns — — — — — — ns — — ns 1997 Microchip Technology Inc. ...
Page 191
... I/O Hi-impedance from MCLR Low IOZ * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. PIC16C6X Min Typ† ...
Page 192
... N = prescale value (2, 4, ..., 256) — ns Must also meet parameter 47 — ns — ns — ns — ns — ns Must also meet parameter 47 — ns — ns — ns — ns — prescale value ( prescale value ( — ns — ns 200 kHz 7Tosc — 1997 Microchip Technology Inc. ...
Page 193
... TccR CCP1 output rise time 54 TccF CCP1 output fall time * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc Min No Prescaler ...
Page 194
... Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234D-page 194 65 62 Min Typ† 20 — PIC16C64 20 — PIC16LC64 35 — — — 10 — 63 Max Units Conditions — ns — ns — 1997 Microchip Technology Inc. ...
Page 195
... SCK output fall time (master mode) 80 TscH2doV, SDO data output valid after SCK TscL2doV edge † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc 75 Min T CY ...
Page 196
... STOP Condition Conditions Only relevant for repeated START condition After this period the first clock pulse is generated 1997 Microchip Technology Inc. ...
Page 197
... This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line T max. + tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I R released. 1997 Microchip Technology Inc. 100 101 107 106 109 ...
Page 198
... PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 NOTES: DS30234D-page 198 1997 Microchip Technology Inc. ...
Page 199
... Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications recommended that the user select the device type that ensures the specifications required. 1997 Microchip Technology Inc. (except V , MCLR, and RA4) ..........................................-0. ...
Page 200
... Rext in kOhm. measurement. +125˚C for extended, +85˚C for industrial and +70˚C for commercial Conditions = 4 MHz, OSC = 5.5V (Note MHz, OSC = 5. 4.0V, WDT enabled 4.0V, WDT disabled + 4.0V, WDT disabled 4.0V, WDT disabled, - +125 and 1997 Microchip Technology Inc. ...