PIC16LF1823-E/P Microchip Technology, PIC16LF1823-E/P Datasheet - Page 197

• Manufacturer Part Number: PIC16LF1823-E/P
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 12 I/0, Enhanced Mid Range Core, N
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1823-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 14-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.5
The signal provided from any selected input source for
the carrier high and carrier low signals can be inverted.
Inverting the signal for the carrier high source is
enabled by setting the MDCHPOL bit of the MDCARH
register. Inverting the signal for the carrier low source is
enabled by setting the MDCLPOL bit of the MDCARL
register.
23.6
Some peripherals assert control over their correspond-
ing output pin when they are enabled. For example,
when the CCP1 module is enabled, the output of CCP1
is connected to the CCP1 pin.
This default connection to a pin can be disabled by set-
ting the MDCHODIS bit in the MDCARH register for the
carrier high source and the MDCLODIS bit in the
MDCARL register for the carrier low source.
23.7
The MDBIT of the MDCON register can be selected as
the source for the modulator signal. This gives the user
the ability to program the value used for modulation.
23.8
The modulator source default connection to a pin can
be disabled by setting the MDMSODIS bit in the
MDSRC register.
23.9
The modulated output signal provided on the MDOUT
pin can also be inverted. Inverting the modulated out-
put signal is enabled by setting the MDOPOL bit of the
MDCON register.
23.10 SLEW RATE CONTROL
The slew rate limitation on the output port pin can be
disabled. The slew rate limitation can be removed by
clearing the MDSLR bit in the MDCON register.
23.11 OPERATION IN SLEEP MODE
The DSM module is not affected by Sleep mode. The
DSM can still operate during Sleep, if the Carrier and
Modulator input sources are also still operable during
Sleep.
 2010 Microchip Technology Inc.
CARRIER SOURCE POLARITY
SELECT
CARRIER SOURCE PIN DISABLE
PROGRAMMABLE MODULATOR
DATA
MODULATOR SOURCE PIN
DISABLE
MODULATED OUTPUT POLARITY
PIC12F/LF1822/PIC16F/LF1823
Preliminary
23.12 Effects of a Reset
Upon any device Reset, the Data Signal Modulator
module is disabled. The user’s firmware is responsible
for initializing the module before enabling the output.
The registers are reset to their default values.
DS41413B-page 197