PIC16LF1823-E/P Microchip Technology, PIC16LF1823-E/P Datasheet - Page 62

• Manufacturer Part Number: PIC16LF1823-E/P
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 12 I/0, Enhanced Mid Range Core, N
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1823-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 14-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC12F/LF1822/PIC16F/LF1823
5.2.2.6
The Internal Oscillator Block can be used with the 4X
PLL associated with the External Oscillator Block to
produce a 32 MHz internal system clock source. The
following settings are required to use the 32 MHz inter-
nal clock source:
• The FOSC bits in Configuration Word 1 must be
• The SCS bits in the OSCCON register must be
• The IRCF bits in the OSCCON register must be
• The SPLLEN bit in the OSCCON register must be
The 4xPLL is not available for use with the internal
oscillator when the SCS bits of the OSCCON register
are set to ‘1x’. The SCS bits must be set to ‘00’ to use
the 4xPLL with the internal oscillator.
DS41413B-page 62
set to use the INTOSC source as the device sys-
tem clock (FOSC<2:0> = 100).
cleared to use the clock determined by
FOSC<2:0> in Configuration Word 1
(SCS<1:0> = 00).
set to the 8 MHz HFINTOSC set to use
(IRCF<3:0> = 1110).
set to enable the 4xPLL, or the PLLEN bit of the
Configuration Word 2 must be programmed to a
‘1’.
Note:
When using the PLLEN bit of the
Configuration Word 2, the 4xPLL cannot
be disabled by software and the 8 MHz
HFINTOSC option will no longer be
available.
32 MHz Internal Oscillator
Frequency Selection
Preliminary
5.2.2.7
When switching between the HFINTOSC, MFINTOSC
and the LFINTOSC, the new oscillator may already be
shut down to save power (see
case, there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC,
MFINTOSC and LFINTOSC oscillators. The sequence
of a frequency selection is as follows:
1.
2.
3.
4.
5.
6.
7.
See
If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected. Clock switching
time delays are shown in
Start-up delay specifications are located in the
oscillator
Specifications”.
IRCF<3:0> bits of the OSCCON register are
modified.
If the new clock is shut down, a clock start-up
delay is started.
Clock switch circuitry waits for a falling edge of
the current clock.
The current clock is held low and the clock
switch circuitry waits for a rising edge in the new
clock.
The new clock is now active.
The OSCSTAT register is updated as required.
Clock switch is complete.
Figure 5-7
tables
Internal Oscillator Clock Switch
Timing
for more details.
of
 2010 Microchip Technology Inc.
Table
Section 30.0
Figure
5-1.
5-7). If this is the
“Electrical