PIC16LF722A-I/SO Microchip Technology, PIC16LF722A-I/SO Datasheet - Page 173

• Manufacturer Part Number: PIC16LF722A-I/SO
• Description: 3.5 KB Flash, 16 MHz Int. Osc, NanoWatt XLP 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF722A-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width), 8 Leads
• Processor Series: PIC16LF
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

17.2.10
When the CKP bit is cleared, the SCL output is held low
once it is sampled low. Therefore, the CKP bit will not
stretch the SCL line until an external I
has already asserted the SCL line low. The SCL output
will remain low until the CKP bit is set and all other
devices on the I
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (Figure 17-14).
FIGURE 17-14:
 2010 Microchip Technology Inc.
SSPCON
SDA
CKP
SCL
WR
CLOCK SYNCHRONIZATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
2
C bus have released SCL. This
CLOCK SYNCHRONIZATION TIMING
DX
2
C master device
Master device
asserts clock
PIC16F/LF722A/723A
17.2.11
While in Sleep mode, the I
addresses of data, and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if SSP interrupt is enabled).
Master device
deasserts clock
SLEEP OPERATION
2
C module can receive
DS41417A-page 173
DX-1