PIC24F32KA301-E/SO Microchip Technology, PIC24F32KA301-E/SO Datasheet - Page 181

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PIC24F32KA301-E/SO

Manufacturer Part Number
PIC24F32KA301-E/SO
Description
32KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, XLP 20 SOIC .300in
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheet

Specifications of PIC24F32KA301-E/SO

Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
32KB (11K x 24)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (0.295", 7.50mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
18.0
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules
available in this PIC24F device family. The UART is a
full-duplex asynchronous system that can communicate
with peripheral devices, such as personal computers,
LIN/J2602, RS-232 and RS-485 interfaces. This module
also supports a hardware flow control option with the
UxCTS and UxRTS pins, and also includes an IrDA
encoder and decoder.
The primary features of the UART module are:
• Full-Duplex, 8-Bit or 9-Bit Data Transmission
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Hardware Flow Control Option with UxCTS and
FIGURE 18-1:
 2011 Microchip Technology Inc.
Note:
through the UxTX and UxRX Pins
UxRTS pins
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended
reference source. For more information
on the Universal Asynchronous Receiver
Transmitter, refer to the “PIC24F Family
Reference Manual”, Section 21. “UART”
(DS39708).
UART SIMPLIFIED BLOCK DIAGRAM
to
be
Hardware Flow Control
Baud Rate Generator
UARTx Transmitter
UARTx Receiver
a
IrDA
comprehensive
®
PIC24FV32KA304 FAMILY
®
• Fully Integrated Baud Rate Generator (IBRG) with
• Baud Rates Ranging from 1 Mbps to 15 bps at
• 4-Deep, First-In-First-Out (FIFO) Transmit Data
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error
• Support for 9-bit mode with Address Detect
• Transmit and Receive Interrupts
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Supports Automatic Baud Rate Detection
• IrDA
• 16x Baud Clock Output for IrDA Support
A simplified block diagram of the UART is shown in
Figure
important hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
16-bit Prescaler
16 MIPS
Buffer
Detection
(9
th
bit = 1)
®
18-1. The UART module consists of these
Encoder and Decoder Logic
UxBCLK
UxRTS
UxCTS
UxRX
UxTX
DS39995B-page 181

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