PIC24F32KA301-E/SO Microchip Technology, PIC24F32KA301-E/SO Datasheet - Page 57

• Manufacturer Part Number: PIC24F32KA301-E/SO
• Description: 32KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, XLP 20 SOIC .300in
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F32KA301-E/SO

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (0.295", 7.50mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.3.3
The upper 32 Kbytes of data space may optionally be
mapped into an 16K word page (in PIC24FV16KA3XX
devices) and a 32K word page (in PIC24FV32KA3XX
devices) of the program space. This provides
transparent access of stored constant data from the
data space without the need to use special instructions
(i.e., TBLRDL/H).
Program space access through the data space occurs
if the MSb of the data space EA is ‘1’ and PSV is
enabled by setting the PSV bit in the CPU Control
(CORCON<2>) register. The location of the program
memory space to be mapped into the data space is
determined by the Program Space Visibility Page
Address (PSVPAG) register. This 8-bit register defines
any one of 256 possible pages of 16K words in
program space. In effect, PSVPAG functions as the
upper 8 bits of the program memory address, with the
15 bits of the EA functioning as the lower bits.
By incrementing the PC by 2 for each program memory
word, the lower 15 bits of data space addresses directly
map to the lower 15 bits in the corresponding program
space addresses.
Data reads from this area add an additional cycle to the
instruction being executed, since two program memory
fetches are required.
FIGURE 4-7:
 2011 Microchip Technology Inc.
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space....
When CORCON<2> = 1 and EA<15> = 1:
PSVPAG
00
READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
PROGRAM SPACE VISIBILITY OPERATION
23
Program Space
15
0
000000h
002BFEh
800000h
PIC24FV32KA304 FAMILY
Although each data space address, 8000h and higher,
maps directly into a corresponding program memory
address (see Figure 4-7), only the lower 16 bits of the
24-bit program word are used to contain the data. The
upper 8 bits of any program space location used as data
should be programmed with ‘1111
0000’ to force a NOP. This prevents possible issues
should the area of code ever be accidentally executed.
For operations that use PSV and are executed outside a
REPEAT loop, the MOV and MOV.D instructions will require
one instruction cycle in addition to the specified execution
time. All other instructions will require two instruction
cycles in addition to the specified execution time.
For operations that use PSV, which are executed inside
a REPEAT loop, there will be some instances that
require two instruction cycles in addition to the
specified execution time of the instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
• Execution upon re-entering the loop after an
Any other iteration of the REPEAT loop will allow the
instruction accessing data, using PSV, to execute in a
single cycle.
Note:
interrupt
interrupt is serviced
Data Space
PSV Area
PSV access is temporarily disabled during
table reads/writes.
0000h
8000h
FFFFh
...while the lower 15 bits
of the EA specify an exact
address within the PSV
area. This corresponds
exactly to the same lower
15 bits of the actual
program space address.
Data EA<14:0>
DS39995B-page 57
1111’ or ‘0000