PIC24FV32KA302T-I/ML Microchip Technology, PIC24FV32KA302T-I/ML Datasheet - Page 159

• Manufacturer Part Number: PIC24FV32KA302T-I/ML
• Description: 32KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, 5V 28 QFN 6x6mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FV32KA302T-I/ML

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad
• Processor Series: PIC24FV
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.3.1
In Edge-Aligned PWM mode, the period is specified by
the value of the OCxRS register. In Center-Aligned
PWM mode, the period of the synchronization source,
such as the Timers’ PRy, specifies the period. The
period in both cases can be calculated using
Equation
EQUATION 15-1:
EQUATION 15-2:
EQUATION 15-3:
 2011 Microchip Technology Inc.
1. Find the OCxRS register value for a desired PWM frequency of 52.08 kHz, where F
2.
Where:
Note 1:
Note 1: Based on T
PWM Period = [Value + 1] x T
clock rate) and a prescaler setting of 1:1 using Edge-Aligned PWM mode:
Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate:
T
PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 s
PWM Period = (OCxRS + 1) • T
19.2 s
OCxRS
PWM Resolution = log
15-1.
Value = OCxRS in Edge-Aligned PWM mode
and can be PRy in Center-Aligned PWM mode
(if TMRy is the sync source).
CY
PWM PERIOD
Based on T
PLL are disabled.
= 2 * T
OSC
Note 1: Based on F
Maximum PWM Resolution (bits) =
CY
= (OCxRS + 1) • 62.5 ns • 1
= 306
CY
CALCULATING THE PWM
PERIOD
CALCULATION FOR MAXIMUM PWM RESOLUTION
PWM PERIOD AND DUTY CYCLE CALCULATIONS
= 62.5 ns
= T
= 2 * T
= (log
= 8.3 bits
OSC
CY
* 2; Doze mode and
10
OSC
(1)
10
x (Prescaler Value)
(F
(16 MHz/52.08 kHz)/log
CY
; Doze mode and PLL are disabled.
/F
CY
PWM
CY
• (OCx Prescale Value)
= F
)/log
OSC
10
PIC24FV32KA304 FAMILY
2) bits
/2, Doze mode and PLL are disabled.
log
10
10
2) bits
(
F
15.3.2
The PWM duty cycle is specified by writing to the
OCxRS and OCxR registers. The OCxRS and OCxR
registers can be written to at any time, but the duty
cycle value is not latched until a period is complete.
This provides a double buffer for the PWM duty cycle
and is essential for glitchless PWM operation.
Some important boundary parameters of the PWM duty
cycle include:
• Edge-Aligned PWM:
• Center-Aligned PWM (with TMRy as the sync
See
Table 15-1
frequencies and resolutions for a device operating at
4 MIPS and 10 MIPS, respectively.
PWM
- If OCxR and OCxRS are loaded with 0000h,
- If OCxRS is greater than OCxR, the pin will
source):
- If OCxR, OCxRS and PRy are all loaded with
- If OCxRS is greater than PRy, the pin will go
the OCx pin will remain low (0% duty cycle).
remain high (100% duty cycle).
0000h, the OCx pin will remain low (0% duty
cycle).
high (100% duty cycle).
• (Prescale Value)
Example 15-3
log
10
F
(2)
PWM DUTY CYCLE
CY
and
OSC
Table 15-2
(1)
(1)
= 8 MHz with PLL (32 MHz device
for PWM mode timing details.
)
bits
show example PWM
DS39995B-page 159