PIC24HJ256GP610A-E/PT Microchip Technology, PIC24HJ256GP610A-E/PT Datasheet - Page 4

• Manufacturer Part Number: PIC24HJ256GP610A-E/PT
• Description: 16 Bit MCU 40MIPS 256KB FLASH 100 TQFP 12x12x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ256GP610A-E/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24HJ256GPX06A/X08A/X10A
4. Module: ADC
5. Module: SPI
6. Module: DMA Controller
DS80482D-page 4
The
(ADxCON1<0>) does not indicate completion of
conversion when External Interrupt is selected as
the ADC trigger source (ADxCON1<SSRC> = 1).
Work around
Use an ADC interrupt or poll ADxIF bit in the IFSx
registers
conversion.
Affected Silicon Revisions
Writing to the SPIxBUF register as soon as the
TBF bit is cleared will cause the SPI module to
ignore the written data. Applications that use SPI
with DMA are not affected by this erratum.
Work around
After the TBF bit is cleared, wait for a minimum
duration of one SPI clock before writing to the
SPIxBUF register.
Alternately, do one of the following:
• Poll the RBF bit and wait for it to get set before
• Poll the SPI Interrupt flag and wait for it to get
• Use an SPI Interrupt Service Routine
• Use DMA
Affected Silicon Revisions
DMA CPU write collisions will not be detected, and
the corresponding XWCOLn bit (n = 0, 1, …, 7) will
not be set. As a result, a CPU write collision event
will not generate a DMA Error Trap.
Work around
None. Before writing to any memory location in
DMA RAM, ensure that none of the enabled DMA
channels is using the same memory location for
data transfers from a peripheral.
Affected Silicon Revisions
A2
A2
A2
X
writing to the SPIxBUF register
set before writing to the SPIxBUF register
X
ADC
A3
A3
A3
X
X
X
to
Conversion
determine
Status
the
completion
(DONE)
bit
of
7. Module: ADC
8. Module: All
If the ADC module is in an enabled state when the
device enters Sleep mode as a result of executing
a PWRSAV #0 instruction, the device power-down
current (I
in the device data sheet. This may happen even if
the ADC module is disabled by clearing the ADON
bit prior to entering Sleep mode.
Work around
In order to remain within the I
listed in the device data sheet, the user software
must completely disable the ADC module by
setting the ADC Module Disable bit in the
corresponding Peripheral Module Disable register
(PMDx), prior to executing a PWRSAV
instruction.
Affected Silicon Revisions
The affected silicon revisions listed below are not
warranted for operation at 150ºC.
Work around
Only use the affected revisions of silicon for Hi-Temp
operating range from -40ºC to +140ºC.
Affected Silicon Revisions
A2
A2
X
X
A3
A3
X
X
PD
) may exceed the specifications listed
© 2010 Microchip Technology Inc.
PD
specifications
#0