XRD5408AID-F Exar Corporation, XRD5408AID-F Datasheet - Page 9

• Manufacturer Part Number: XRD5408AID-F
• Description: Low Power 8-Bit DAC With Serial Input
• Manufacturer: Exar Corporation

Specifications of XRD5408AID-F

• Settling Time: 13µs
• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 155mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The DACs are programmed by a 16 bit word of serial data.
The format of the serial input register is shown in Figure 6.
The leading 4 bits are not used to update the DAC. If the
DAC is not daisy-chained then only a 12 bit serial word is
needed to program the DAC. The next 8, 10 or 12 bits
after the 4 leading bits are data bits. The XRD5408’s first
8 bits are valid data and the trailing 4 bits must be set to 0.
Figure 7 demonstrates the 16 bit digital word for the 8,
10,12 bit DACs.
SCLK should be held low when CS transitions low. Data is
clocked in on the rising edge of SCLK when CS is low.
SDIN data is held in a 16 bit serial shift register. The DAC
is updated with the data bits on the rising edge of CS.
When CS is high data is not shifted into the
XRD5408/10/12.
Daisy-Chaining
The digital output port (DOUT) has a 4mA drive for greater
fan-out capability when daisy-chaining. DOUT allows
cascading of multiple DACs with the same serial data
stream. The data at SDIN appears at DOUT after 16 clock
cycles plus one clock width (t
(t
CS is high. DOUT changes on the falling edge of SCLK
when CS is low.
Any number of DACs can be connected in this way by
connecting DOUT of one DAC to SDIN of the next DAC.
Table 2. 16-Bit Digital Word Register for XRD5408,
DO
XRD5412
XRD5410
XRD5408
). DOUT remains in the state of the last data bit when
Part
Rev. 1.20
SDIN
Leading
Unused
XXXX
XXXX
XXXX
Bits
XRD5410, XRD5412.
MSB
CH
XXXXXXXX
XXXXXXXX
XXXXXXXX
Data Bits
) and a propagation delay
Figure 6. Shift Register Format
LSB
DAC
Trailing
None
0000
Bits
“0”
00
n
9
AC
AC Feedthrough from V
low impedance grounding as shown in Figure 7. If the
DAC data is set to all “0”s then V
divider between the DAC string impedance and ground
impedance.
section for recommendations.
feedthrough for a 1kHz 2Vpp signal with code = 0 is
-80dB.
Compatible with MAX515 & MAX539
The XRD5408/10/12 family of DACs are functionally
campatible with the MAX515 & MAX539 while providing
significant improvements. The XRD5408/10/12 DACs
have lower power, faster serial ports, and a constant
reference impedance to minimize the reference driving
requirements and maximize system linearity. The DOUT
FT
V
Feedthrough (DAC Code = 0)
Figure 7. AC
REFIN
RGND
Analog GND
R
IN
GND
See the Power Supply and Grounding
MSB
Circuit, DAC Code =0
FT
X
Feedthrough Equivalent
REFIN
X
+
--
to V
X
OUT
XRD5408/10/12
OUT
X
is a function of the
The typical AC
is minimized with
DOUT
V
OUT