ADV7176AKS Analog Devices Inc, ADV7176AKS Datasheet - Page 27

• Manufacturer Part Number: ADV7176AKS
• Manufacturer: Analog Devices Inc

Specifications of ADV7176AKS

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Not Compliant

TTXREQ CONTROL REGISTER TC07 (TC07–TC00)
(Address [SR4–SR0] = 24H)
Teletext Control Register is an 8-bit-wide register.
TTXREQ Rising Edge Control (TC07–TC04)
These bits control the position of the rising edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles—see Figure 48.
CVBS: Composite Video Baseband Signal
Y:
C:
U:
V:
R:
G:
B:
Input Default Color (MR36)
This bit determines the default output color from the DACs for
zero input data (or disconnected). A Logical “0” means that the
color corresponding to 00000000 will be displayed. A Logical “1”
forces the output color to black for 00000000 input video data.
MR06
0
0
0
0
1
1
1
1
Luminance Component Signal (For YUV or Y/C Mode)
Chrominance Signal (For Y/C Mode)
Chrominance Component Signal (For YUV Mode)
Chrominance Component Signal (For YUV Mode)
RED Component Video (For RGB Mode)
GREEN Component Video (For RGB Mode)
BLUE Component Video (For RGB Mode)
MR26
0
0
1
1
0
0
1
1
MR37
0
1
0
1
0
1
0
1
MR37
0
1
INPUT DEFAULT COLOR
MR37
MR36
TC07
COMPOSITE
GREEN/LUMA/Y
TC07 TC06
0
1
0
0
"
1
1
TTXREQ RISING EDGE CONTROL
DAC A
INPUT COLOR
BLACK
DAC A
CVBS
Y
CVBS
Y
CVBS
G
CVBS
Y
0
0
1
1
"
MR36
TC06
TC05 TC04
Table I. DAC Output Configuration Matrix
0
0
1
1
"
BLUE/COMP/U
BLUE/COMP/U
BE WRITTEN TO
ZERO SHOULD
DAC OUTPUT
SWITCHING
DAC B
MR35 = 0
THIS BIT
0
1
"
0
1
MR35
TC05
MR34
DAC B
CVBS
CVBS
CVBS
CVBS
B
B
U
U
TELETEXT ENABLE
0
1
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
RED/CHROMA/V
RED/CHROMA/V
MR34
DISABLE
ENABLE
TC04
DAC C
DAC Output Switching (MR37)
This bit is used to switch the DAC outputs from SCART to a
EUROSCART configuration. A complete table of all DAC
output configurations is shown below.
NOTE
Each DAC can be individually powered ON or OFF with the following control bits
(“0” = ON, “1” = OFF):
TTXREQ Falling Edge Control (TC03–TC00)
These bits control the position of the falling edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles. This controls the active window for teletext
data. Increasing this value reduces the amount of teletext bits
below the default of 360. If bits TC03–TC00 are unchanged
when bits TC07–TC04 are changed, the falling edge of TTXREQ
will track that of the rising edge (i.e., the time between the fall-
ing and rising edge remains constant)—see Figure 48.
MR33
TC03
TC03 TC02
MR13 - DAC C
MR14 - DAC D
MR15 - DAC B
MR16 - DAC A
GREEN/LUMA/Y
COMPOSITE
0
0
"
1
1
RESERVED
TTXREQ FALLING EDGE CONTROL
DAC C
C
C
C
C
R
R
V
V
DAC D
0
0
"
1
1
MR32
TC02
TC01 TC00
MR31
0
0
1
1
"
VBI PASSTHROUGH
0
1
0
1
"
0
1
DISABLE
ENABLE
MR31
TC01
DAC D
Y
CVBS
Y
CVBS
G
CVBS
Y
CVBS
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
(READ ONLY)
ADV7175A/ADV7176A
REV CODE
MR30
MR30
TC00
Simultaneous Output
2 Composite and Y/C
2 Composite and Y/C
2 Composite and Y/C
2 Composite and Y/C
RGB and Composite
RGB and Composite
YUV and Composite
YUV and Composite