LTC1553LCSW#TRMPBF Linear Technology, LTC1553LCSW#TRMPBF Datasheet - Page 17

• Manufacturer Part Number: LTC1553LCSW#TRMPBF
• Manufacturer: Linear Technology

Specifications of LTC1553LCSW#TRMPBF

• Lead Free Status / RoHS Status: Compliant

APPLICATIONS
Table 6 shows the suggested compensation components
for 5V input applications based on the inductor and output
capacitor values. The values were calculated using mul-
tiple paralleled 330 F AVX TPS series surface mount
tantalum capacitors as the output capacitor. The optimum
component values might deviate from the suggested
values slightly because of board layout and operating
condition differences.
An alternate output capacitor is the Sanyo MV-GX series.
Using multiple parallel 1500 F Sanyo MV-GX capacitors
for the output capacitor, Table 7 shows the suggested
compensation component value for a 5V input application
based on the inductor and output capacitor values.
Table 7. Suggested Compensation Network for 5V Input
Application Using Multiple Paralleled 1500 F SANYO MV-GX
Output Capacitors
VID0 to VID4, PWRGD and FAULT
The digital inputs (VID0 to VID4) program the internal DAC
which in turn controls the output voltage. These digital
input controls are intended to be static and are not
designed for high speed switching. Forcing V
from a high to a low voltage by changing the VID
quickly can cause FAULT to trip.
Figure 9 shows the relationship between the V
PWRGD and FAULT. To prevent PWRGD from interrupting
the CPU unnecessarily, the LTC1553L has a built-in t
delay to prevent noise at the SENSE pin from toggling
PWRGD. The internal time delay is designed to take about
500 s for PWRGD to go low and 1ms for it to recover.
Once PWRGD goes low, the internal circuitry watches for
the output voltage to exceed 115% of the rated voltage. If
L
O
2.7
2.7
2.7
5.6
5.6
5.6
( H)
1
1
1
C
4500
6000
9000
4500
6000
9000
4500
6000
9000
O
( F)
U
R
INFORMATION
C
U
4.3
5.6
8.2
11
15
22
24
30
47
(k )
W
C
0.0047
0.0047
0.0047
0.022
C
0.01
0.01
0.01
0.01
0.01
( F)
OUT
OUT
U
C1 (pF)
voltage,
270
220
150
100
PWRBAD
82
56
56
39
27
to step
n
pins
this happens, FAULT will be triggered. Once FAULT is
triggered, G1 and G2 will be forced low immediately and
the LTC1553L will remain in this state until V
supply is recycled or OUTEN is toggled.
LAYOUT CONSIDERATIONS
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1553L. These items are also illustrated graphically in
the layout diagram of Figure 10. The thicker lines show the
high current paths. Note that at 10A current levels or
above, current density in the PC board itself is a serious
concern. Traces carrying high current should be as wide
as possible. For example, a PCB fabricated with 2oz
copper requires a minimum trace width of 0.15
carry 10A.
1. In general, layout should begin with the location of the
2. The GND and SGND pins should be shorted right at the
RATED V
power devices. Be sure to orient the power circuitry so
that a clean power flow path is achieved. Conductor
widths should be maximized and lengths minimized.
After you are satisfied with the power path, the control
circuitry should be laid out. It is much easier to find
routes for the relatively small traces in the control
circuits than it is to find circuitous routes for high
current paths.
LTC1553L. This helps to minimize internal ground
disturbances in the LTC1553L and prevents differences
in ground potential from disrupting internal circuit
operation. This connection should then tie into the
PWRGD
FAULT
–5%
15%
OUT
5%
t
PWRBAD
Figure 9. PWRGD and FAULT
V
OUT
t
PWRGD
t
FAULT
LTC1553L
1553L F09
CC
17
power
"
to