TS86101G2BCGL E2V, TS86101G2BCGL Datasheet
TS86101G2BCGL
Specifications of TS86101G2BCGL
Related parts for TS86101G2BCGL
TS86101G2BCGL Summary of contents
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... C grade: 0°C < < 90° – V grade: –40°C < < 110° – M grade: –55°C < < 125° e2v semiconductors SAS 2009 4:1 10-bit 1.2 Gsps MUXDAC L TS86101G2B Visit our website: www.e2v.com for the latest version of the datasheet 0992D–BDC–04/09 ...
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... Moisture Characteristics” on page TS86101G2B Value Unit GND to 6.0 V –6.0 to GND V –6.0 to GND V 0 > –0. < 5 < 1 > –0. < 5 < 1 > –3 < 0. < 1 GND CCD 135 °C –65 to 150 °C 250 (during 10s max.) °C 36.) e2v semiconductors SAS 2009 ...
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... Note and V are internally short circuited through the chip substrate (4Ω equivalent resistance between V EAA EED Therefore, V and V EEA EED short circuited, and power supply connected to the V e2v semiconductors SAS 2009 Symbol Comments V CCD V EED V EEA <Y0_T; Y9_T> <Y0_F; Y9_F> D_CK_T ...
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... J Typ Max Unit 10 bits –5 –4.75 V –5 –4.75 V 380 430 mA 300 340 mA 3.6 4.0 W 1.0 2.7 V 1.4 2.9 V 0.2 0.7 Vp 1.2 2 Ω 50 Ω 100 capacitors) 0.3 0.8 Vp 0.15 0 dBm 2 dBm 2 pF Ω 50 Ω 100 e2v semiconductors SAS 2009 ...
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... Spurious free dynamic range : Fs = 600 Msps; Fout = 12.5 MHz (–6 dBFS 600 Msps; Fout = 287.5 MHz (–6 dBFS 1.2 Gsps; Fout = 25 MHz (–6 dBFS 1.2 Gsps; Fout = 575 MHz (–6 dBFS) e2v semiconductors SAS 2009 = 5V, V and V = –5V, LVDS Input Level, T CCD EEA ...
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... LVDS Input Level 85°C J Min Typ Max ±3 –80 – 0.25 –0.25 0.25 –0.25 ±3.5% ±2.3% ±1.5% –400 –600 e2v semiconductors SAS 2009 Unit dBc dBFS dBc dBFS dB dBm dBm dBFS dBFS dBFS dB LSB LSB LSB LSB %FS %FS %FS ppm/°C mV ...
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... DC gain dispersion excludes initial gain error. 5. Mid-scale output voltage is measured with a 100Ω differential load on DAC output. 6. Minimum operating clock frequency can be DC. Actually linked to clock input AC coupling external capacitor. e2v semiconductors SAS 2009 = 5V, V and V = –5V, LVDS Input Level, T ...
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... Level Min – (at 350 MWord/ 22 35. TS86101G2B Typ Max 300 ps peak- to- peak 500 ps 500 ps 350 MWords/s 1400 MHz 1 ps rms 2 clock cycle 5 clock cycle 0 to 3.1 ns 200 ps 600 ps 1 clock cycle 3.7 ns Pipeline delay + TOD 180 ps e2v semiconductors SAS 2009 ...
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... Fout-dependent. For example, considering the SFDR with a –10 dBFS digital sinusoidal input and Fout = 499 MHz Gsps, the differential output power level of the single tone at Fout = 499 MHz is –6.9 dBm (–10 dBFS = –3 dBm and the theoretical deviation of sin X/X is –3 Nyquist). e2v semiconductors SAS 2009 Characteristics ° ...
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... Fs (MHz) 400 600 800 1000 Fs (MHz) TS86101G2B -6dBFS -12dBFS -16dBFS SFDR = 58 dBc / 68 dBFS (-6dBFS) SFDR = 53 dBc / 68 dBFS (-12dBFS) SFDR = 47 dBc / 67 dBFS (-16dBFS) 1200 1400 -6 dBFS 1200 1400 -12 dBFS -16 dBFS e2v semiconductors SAS 2009 ...
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... Single-tone Spectrum in First Nyquist Fs = 1.2 Gsps in First Nyquist Zone (Fout = 575 MHz, Ref 10 dBm SWP Center 300 MHz e2v semiconductors SAS 2009 6 dBFS) SFDR = 62 dBc (68 dBFS) – * RBW 5 kHz VBW 5 MHz * Att 30 dB SWT 24s * dBm 60 MHz/ 6 dBFS) SFDR = 59 dBc (69 dBFS) – * RBW 5 kHz ...
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... Nyquist Zone 1350 450 600 900 1200 1500 Fs Fs Fs/4 Fs Fout (MHz) TS86101G2B 4th Nyquist Zone Frequency Domain Time Domain - GHz 5. 4th Nyquist Zone 1650 1800 2100 2400 3 Fs/4 4th Nyquist Zone 1650 1800 2100 2400 3 Fs e2v semiconductors SAS 2009 ...
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... The absolute level of harmonics is equivalent in both the first and third Nyquist zones. The SFDR figures (in dBFS) are therefore similar in these two Nyquist zones. This shows that the MUXDAC can be used equivalently in the first and third Nyquist zones with equivalent performances (see 14). e2v semiconductors SAS 2009 RBW 5 kHz * VBW 5 MHz ...
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... Nyquist Fout = 450 MHz Fout = Fs + 150 MHz 600 1200 Fout (MHz) * RBW 5 kHz VBW 5 MHz * Att 30 dBm SWT dBm 60 MHz/ TS86101G2B 3rd Nyquist SFDR 1st Nyquist SFDR Fout = Fs + 450 MHz 1800 Span 600 MHz e2v semiconductors SAS 2009 ...
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... Figure 3-12. Noise Power Ratio (NPR 1.2 Gsps 580 MHz Broadband Pattern, 25 MHz Notch Centered Around 250 MHz at Loading Factor, NPR = 49 dB Ref -10 dBM Start 0 Hz e2v semiconductors SAS 2009 18 dBFS): Fout1 = 80 MHz, Fout2 = 142.5 MHz, Fout3 = 205 MHz, Fout4 = 267.5 MHz, – * RWB 5 kHz ...
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... Fs = 1.2 Gsps 580 MHz Broadband Pattern, 25 MHz Notch Centered Around 250 MHz Fs = 1.4 Gsps 680 MHz Broadband Pattern, 25 MHz Notch Centered Around 250 MHz -35 -30 16 0992D–BDC–04/09 -25 -20 -15 Peak to RMS Loading Factor (dB) TS86101G2B 12 dBFS. – @1.4 GSPS ' @1.2 GSPS ' -10 -5 e2v semiconductors SAS 2009 ...
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... Pin Description Figure 4-1. TS86101G2B Pin Configuration (Top View) No ball/column on A1 Index Corner e2v semiconductors SAS 2009 TS86101G2B 17 0992D–BDC–04/09 ...
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... C9_T is the MSB Inverted phase (-) digital inputs C0_F is the inverted LSB C9_F is the inverted MSB In-phase (+) digital input Port D D0_T is the LSB D9_T is the MSB Inverted phase (-) digital inputs D0_F is the inverted LSB D9_F is the inverted MSB e2v semiconductors SAS 2009 ...
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... Analog Outputs OUT_T OUT_F Clock Inputs D_CK_T D_CK_F CW_IN_T CW_IN_F DSP Clock Outputs DSP_CK_T DSP_CK_F Additional Functions CS_0, CS_1, CS_2, CS_3 DIODE GA Ref TP e2v semiconductors SAS 2009 Pin number T10 R12, T12, R13, T13 T15 P16 R16 A16 TS86101G2B Function In-phase (+) analog output signal ...
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... Differential input data port D Differential analog output Differential Data Ready clock inputs Differential DSP clock output Differential independent master clock input Shift select for DSP clock (TTL) Die junction temperature monitoring Gain adjust (to be connected to the REF pin) e2v semiconductors SAS 2009 ...
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... CW_IN master clock divided by 4. For correct operation, a phase relation between Data Ready and the CW_IN master clock input must be respected (see Figure 5-2. Data or Data Ready (D-CK) Timing D_CK AOUT e2v semiconductors SAS 2009 DGND A0_T; A9_T 20 A0_F; A9_F B0_T; B9_T 20 B0_F ...
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... Tsetup 1.2 ns max allowed allowed forbidden Figure 5-4 on page 22). Within this forbidden zone, the data is stored in the CW_IN D_CK Forbidden area for rising edge of D_CK = 600 ps max TS86101G2B Thold Thold Tsetup allowed forbidden forbidden 2 e2v semiconductors SAS 2009 Tsetup ...
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... F(DSP_CK) is the frequency of the DSP output clock – F(D_CK) is the frequency of the Data Ready input clock Since this input MUX is not programmable, all four ports must be used for proper operation of the DAC. e2v semiconductors SAS 2009 Figure 8-2 on page 30). ...
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... All MUXDAC clock paths within a given DSP should be designed according to the standard high-speed design rules. 24 0992D–BDC–04/09 /V <–2.5V). EEA EED TS86101G2B ramp-up, (up EED /V exceed 90% of EED EEA e2v semiconductors SAS 2009 ...
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... DSP clock. This delay is controlled via the CS_0, CS_1, CS_2 and CS_3 bits and has a range of 3 200 ps discrete steps. Please also refer to The [CS_0;3] bits are TTL signals (1 = TTL high, 10 kΩ or left open TTL low or ground via 10Ω or less) but can also be implemented as shown in e2v semiconductors SAS 2009 Power up End of reset 0V 100% ...
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... Once the diode-mounted transistor is measured, Vbe values according to the junction temperature are given in 26 0992D–BDC–04/09 Open or GND CS_0 Control Open or GND FPGA CS_3 Control Diode Pin Figure 6-5 on page 27. TS86101G2B CS_0 MUXDAC GND CS_3 GND V Protection Diodes e2v semiconductors SAS 2009 ...
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... GA Pin The GA pin (P16) must be connected to the REF pin (R16) with the shortest possible trace between the two balls/columns as depicted in Figure 6-6. GA Pin e2v semiconductors SAS 2009 Figure 6-6. RE (R16 Pitch = 1.27 mm ...
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... Block Diagram Figure 7-1. Block Diagram 28 0992D–BDC–04/09 TS86101G2B e2v semiconductors SAS 2009 ...
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... Vpp Single on 50Ω VPP Differential on 100Ω TOD Includes Internal Propagation Delay: (Phi4, Tconv and Package Propagation Delay) Note: All timing parameters are defined under e2v semiconductors SAS 2009 Tsetup Thold TCW Jitter = 300 ps p.p. max Shift Range: 3.1 ns 0000 ...
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... Data Data Data Data Data Data N -1 Propagation Delay TPD = Pipeline Delay + TOD = 1 Clock Cycle + TOD “Definitions of Terms” on page TS86101G2B Data In Data Ready 1111 % Clock Shift Select Shift DSP Clock Out Data Data Full-scale Step Data 35. e2v semiconductors SAS 2009 ...
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... Equivalent Digital Input Circuit and ESD Protections (Input Data and Data Ready Input Clock) VCCD A0-9_T B0-9_T C0-9_T D0-9_T or D_CK_T A0-9_F DGND B0-9_F C0-9_F D0-9_F or D_CK_F e2v semiconductors SAS 2009 ESD 1.2 KV -0. VEED VCCD VEED VEED ESD 1.2 KV -0. 5.5V VEED DGND TS86101G2B 300Ω ...
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... Equivalent CW_IN Master Input Clock Circuit and ESD Protections AGND 3.5V -0.455 V CW_IN_T -0.5V CW_IN_F 450Ω 500Ω 6V VEEA VEEA 32 0992D–BDC–04/09 AGND 3.5V VEEA VEEA 50Ω AGND 50Ω 6V VEEA TS86101G2B ESD 1.4 KV -0. 300Ω 300Ω ESD 1.6 KV -0. 135 fF e2v semiconductors SAS 2009 ...
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... Figure 9-3. Equivalent DSP Clock Output Buffer and ESD Protections ESD 1.2 KV -0. VEED DSP_CK_T ESD 1.2 KV -0. VEED e2v semiconductors SAS 2009 VCCD 50Ω 50Ω 5.5V 5.5V DGND TS86101G2B ESD 1.2 KV -0. 5.5V VEED ESD 1.2 KV -0. 5.5V VEED 0992D–BDC–04/09 ...
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... ESD 1.2 KV -0. VEEA AOUT_T ESD 1.4 KV -0.3V .. 5.5V 136 fF 5.5V 34 0992D–BDC–04/09 AGND 50Ω 50Ω 5.5V Current Switches Array VEEA VEEA TS86101G2B ESD 1.2 KV -0. 5.5V VEEA ESD 1.4 KV -0.3V .. 5.5V 136 fF 5.5V VEEA e2v semiconductors SAS 2009 AOUT_F ...
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... TSetup Set-up Time (VSWR) Voltage Standing Wave Ratio e2v semiconductors SAS 2009 Description The ratio in dB between the power in the adjacent channel and the power in the channel carrying the modulated signal The maximum deviation in the output step size from the ideal value of one least significant bit (LSB). A DNL of – ...
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... Reduction (result using SPICE, thermal to electrical equivalent model) 0.80 Silicon 0.8 Junction 2.6 4.1 2.8 0.6 0.3 0.4 0.9 0.7 0.4 Infinite heat sink Infinite heat sink at bottom of balls at bottom of balls e2v semiconductors SAS 2009 3.85˚C/Watt ® ...
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... The TS86101G2B MUXDAC features three different power supplies (V two different ground planes (analog ground plane AGND and digital ground plane DGND). We highly recommend that the analog and digital planes be fully separated (both at board level and externally). e2v semiconductors SAS 2009 Silicon Junction Top of lid 0.4˚ ...
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... Bypassing and Grounding Scheme PC Board Analog -5V 1 μF PC Board Analog AGND and V Bypassing and Grounding Scheme CCD 1 μF 1 μF 100 pF VCCD 100 DGND TS86101G2B VEED 100 DGND TS86101G2B VEEA 100 pF VCCD 100 pF VEED VEEA VEEA 100 pF 10nF AGND AGND e2v semiconductors SAS 2009 ...
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... Rule of thumb for determining R and VTT: (VOL-VTT)/R>Swing/100 Figure 12-5. Differential 2.5V PECL + 2.5V PECL Open Emitter Driver VOH = 1.6V VOL = 0.8V Note: Recommended values for R and VTT: VTT = GND 50Ω e2v semiconductors SAS 2009 Z = 50Ω 50Ω VTT Z = 50Ω 50Ω VTT ...
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... When used in single-ended mode, the associated false signal must be tied to the common mode voltage of the true signal, as shown in 40 0992D–BDC–04/ 50Ω 50Ω MUXDAC 50Ω Lines Package Pins Figure 12-7. TS86101G2B MUXDAC Data Input/Data Ready Input 50Ω 50Ω GND 50Ω DGND e2v semiconductors SAS 2009 ...
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... Three configurations are depicted: • The load has a high impedance input buffer • The load has a 100Ω differential buffer • The DSP_CLK is sent to the load via a driver e2v semiconductors SAS 2009 -10 dBm (200 mVpp dBm (800 mVpp) max ...
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... Even without 100Ω differential resistor, the impedance of the output buffer is sufficient. In that case the swing of DSP output clock is twice larger and common mode remains unchanged. 42 0992D–BDC–04/ DSP_CK_T 50Ω Lines 100Ω DSP_CK_F 1.5V As close as possible to the load TS86101G2B 3.3V Load 100 KΩ High Impedence 1 KΩ GND e2v semiconductors SAS 2009 ...
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... Figure 12-12. DSP Output Clock Implementation (General Case, Values Given for Information Only) VCCD 50Ω DGND Note: 1. For reference only, MC100EP17 (for a translation to PECL standard level on DSP_CLK) or NBSG16 drivers from On Semiconductor 2. The 100Ω differential resistor is not mandatory see note e2v semiconductors SAS 2009 MUXDAC DSP_CK_T 50Ω Lines DSP_CK_F MUXDAC DSP_CK_T 50Ω Lines 100Ω ...
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... Line OUT_F 50Ω Line 100 nF TS86101G2B 100 nF 100 nF 50Ω AGND Balun 2 1/sqrt2 50Ω Line ANALOG OUT 7 dBm full-scale output power 50Ω termination AGND e2v semiconductors SAS 2009 ANALOG OUT_T ANALOG OUT_F 4 dBm full-scale output power (each single-ended output) ...
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... Figure 12-15. Interfacing with a Digital Signal Processor DSP -4 dBm (400 mVpp dBm (1.6 Vpp) Single-ended AC-coupled Sine Wave 50Ω Note: All the data and clock inputs/outputs are connected via 50Ω impedance lines. e2v semiconductors SAS 2009 VCC DGND VEED AGND DSP_CK_T TS86101G2B DSP_CK_F 10 A0_T… ...
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... Mechanical Description of CBGA 255 Package Figure 13-1. CBGA 255 Package Outline –Top View No ball index corner Package Chamfer 0.4 (x4) 46 0992D–BDC–04/09 (1.27) 21.00 +/- 0. 255 0.80 +/- 0.10 mm (Position of array of balls/edges A and B) (Position of balls within array) TS86101G2B B e2v semiconductors SAS 2009 ...
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... Figure 13-2. CBGA 255 Package Outline – Side View For lead free roadmap, please contact your local e2v sales office. e2v semiconductors SAS 2009 Balls Eutectic Solder Sn63Pb37 0.80 mm +/- 0.10 0.43 mm 0.65 +/- 0.10 +/- 0.05 1.80 mm +/- 0.15 2.88 mm +/- 0.29 All units in mm ...
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... TS86101G2B Metallic lid 0.381 mm thickness 2 16.64 mm lid (Kovar, Ni-Au plated) Grounded Hermetically soldered to package 0.40 0.20 0.25 0.20 0.50 AI203 Ceramic Balls Package Eutectic Solder Sn63Pb37 Balls Eutectic Solder Sn63Pb37 e2v semiconductors SAS 2009 0.10 0.15 ...
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... Mechanical Description of CI-CGA 255 Package Figure 14-1. CI-CGA 255 Package Outline - Top View No column Index corner SCI Chanfer Package Chanfer 0.4 (x4) SCI Chanfer 0.4 (x3) e2v semiconductors SAS 2009 Top View (1.27) 21.00 +/- 0.20 mm -A- 255x D=0.89+/-0. 0.15 T (Position of columns within array) ...
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... Figure 14-2. CI-CGA 255 Package Outline - Side View 50 0992D–BDC–04/ AI203 AI203 Columns High T Solder Pb/Sn 90/10 0.150 mm (1.62) (0.30 +/- 0.05) 1.800 mm 2.070 mm +/-0.15 +/-0.125 4.30 mm +/- 0.28 All units in mm TS86101G2B e2v semiconductors SAS 2009 ...
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... MUXDAC device (CBGA-255 package), an FPGA chip, a serial interface and a user interface. The TSEV86101G2BGL evaluation kit contains all necessary software and hardware for setting up the board and performing its characterization. e2v semiconductors SAS 2009 Differential Data Bus 80 Bits 10 b ...
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... A thermal system above the evaluation board enables testing of the MUXDAC against temperature variations • An oscilloscope helps define the time domain characteristics of the MUXDAC • A spectrum analyzer helps locate/identify the MUXDAC’s FFTs 17. Ordering Information Part Number Package TS86101G2BCGL CBGA 255 TS86101G2BVGL CBGA 255 TS86101G2BMGS CI-CGA 255 TSEV86101G2BGL CBGA 255 For lead free roadmap, please contact your local e2v sales office ...
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... These products are not designed for use in life support appliances, devices or systems where malfunc- tion of these products can reasonably be expected to result in personal injury. e2v customers using or selling these products for use in such applications their own risk and agree to fully indemnify e2v for any damages resulting from improper use or sale. ...
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... Block Diagram ........................................................................................ 28 8 Timing Diagram ...................................................................................... 29 9 Equivalent Input/Output Schematics ................................................... 31 10 Definitions of Terms .............................................................................. 35 11 Thermal and Moisture Characteristics ................................................ 36 12 Applying the TS86101G2B MUXDAC ................................................... 37 12.1 Accessing Power Supplies .................................................................................. 37 12.2 Digital Inputs and Data Ready Signal Implementation ........................................ 39 e2v semiconductors SAS 2009 TS86101G2B i 0992D–BDC–04/09 ...
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... Interfacing the TS86101G2B MUXDAC with a Digital Signal Processor ............. 45 13 Mechanical Description of CBGA 255 Package .................................. 46 14 Mechanical Description of CI-CGA 255 Package ................................ 49 15 TSEV86101G2BGL Evaluation Kit ........................................................ 51 16 Test Bench Description ......................................................................... 52 17 Ordering Information ............................................................................. 52 18 Appendix ................................................................................................ 53 18.1 Life Support Applications ..................................................................................... 53 ii 0992D–BDC–04/09 TS86101G2B e2v semiconductors SAS 2009 ...
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... Whilst e2v has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v accepts no liability beyond that set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein ...
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... TS86101G2B e2v semiconductors SAS 2009 ...