W9751G6JB-3 Winbond, W9751G6JB-3 Datasheet - Page 4

• Manufacturer Part Number: W9751G6JB-3
• Manufacturer: Winbond
• Type: DDR2 SDRAMr

Specifications of W9751G6JB-3

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 14b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: WBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 150mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

1. GENERAL DESCRIPTION
The W9751G6JB is a 512M bits DDR2 SDRAM, organized as 8,388,608 words × 4 banks × 16 bits.
This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for general
applications. W9751G6JB is sorted into the following speed grades: -18, -25, 25I, 25A and -3. The -18
is compliant to the DDR2-1066 (7-7-7) specification. The -25/25I/25A are compliant to the DDR2-800
(5-5-5) or DDR2-800 (6-6-6) specification (the 25I industrial grade and 25A automotive grade which is
guaranteed to support -40°C ≤ T
specification.
All of the control and address inputs are synchronized with a pair of externally supplied differential
clocks. Inputs are latched at the cross point of differential clocks (CLK rising and CLK falling). All
I/Os are synchronized with a single ended DQS or differential DQS- DQS pair in a source
synchronous fashion.
2. FEATURES
Power Supply: V
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and CLK )
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges
of DQS
Posted CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal
quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
Packaged in WBGA 84 Ball (8X12.5 mm
DD
, V
DDQ
= 1.8 V ± 0.1 V
CASE
≤ 95°C). The -3 is compliant to the DDR2-667 (5-5-5)
2
), using Lead free materials with RoHS compliant
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Publication Release Date: Jun. 18, 2010
W9751G6JB
Revision A03