SL64G6F32M8G-A75AVU STEC, SL64G6F32M8G-A75AVU Datasheet - Page 4

• Manufacturer Part Number: SL64G6F32M8G-A75AVU
• Manufacturer: STEC

Specifications of SL64G6F32M8G-A75AVU

• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 144SODIMM
• Device Core Size: 64b
• Organization: 32Mx64
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 548mA
• Number Of Elements: 8
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Pin Count: 144
• Mounting: Socket
• Lead Free Status / RoHS Status: Compliant

SL64G6F32M8G-A75xVU
SERIAL PRESENCE DETECT INFORMATION
Serial PD Interface Protocol: I
Byte #
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
11
0
1
2
3
4
5
6
7
8
9
Function Described
# of bytes written into serial memory
at module manufacturer
Total # of bytes of SPD memory device
Fundamental memory type
# of row addresses on this assembly
# of column addresses on this assembly
# of module ranks on this assembly
Data width of this assembly
…Data width of this assembly (continued)
Voltage interface standard of this assembly
SDRAM cycle time at CL=3 (t
SDRAM access time from clock at CL=3 (t
DIMM configuration type
Refresh rate/type
SDRAM width
Error Checking DRAM data width
Min. CLK delay for back-to-back rand. col. addr.
SDRAM device attributes: burst lengths
supported
SDRAM device attributes: # of banks on
SDRAM device
SDRAM device attributes: CAS latency
SDRAM device attributes: CS latency
SDRAM device attributes: Write latency
SDRAM module attributes
SDRAM device attributes: general
Minimum clock cycle time at CL=2 (t
Max. data access time form clock at CL=2 (t
Minimum clock cycle time at CL=1 (t
Max. data access time from clock at CL=1 (t
Minimum row precharge time (t
Minimum row active to row active delay (t
Minumum RAS to CAS (t
Minumum RAS pulse width (t
Module bank density
Min. command and address signal setup time (t
Min. command and address signal hold time (t
Min. data signal input setup time (t
2
C; Current sink capability of SDA driver ≤3mA; Maximum clock frequency: 100 KHz
RCD
RAS
)
CYC
RP
)
)
)
DS
CYC
CYC
)
)
)
RRD
AC
AC
AC
)
)
AH
)
)
AS
(Serial Presence Detect Information continued on the next page)
)
)
Document Part Number 61000-01667-105 August 2007 Page 4
V
non-buff., non-reg., non-PLL
Option A
CC
7.5ns
5.4ns
Function Supported
10ns
20ns
15ns
20ns
45ns
1,2,4,8, and full page
6ns
10%, B/R, S/W, P/A, A/P
—
—
256Bytes (2K-bit)
7.8μs, Self-refresh
CAS latency = 2,3
Write Latency = 0
CS latency = 0
t
CCD
128 bytes
SDRAM
2 ranks
64 bits
LVTTL
4 banks
128MB
1.5ns
0.8ns
1.5ns
16 bits
none
none
13
—
9
=1 CLK
Option D
7.5ns
5.4ns
7.5ns
5.4ns
15ns
15ns
15ns
45ns
—
—
144-PIN SO-DIMM
Option A
2Dh
75h
54h
A0h
60h
00h
00h
14h
0Fh
14h
Hex Value
0Dh
8Fh
0Eh
80h
08h
04h
09h
02h
40h
00h
01h
00h
82h
10h
00h
01h
04h
06h
01h
01h
00h
20h
15h
08h
15h
Option D
0Fh
0Fh
0Fh
2Dh
75h
54h
75h
54h
00h
00h