MCIMX27MJP4A Freescale, MCIMX27MJP4A Datasheet - Page 73

• Manufacturer Part Number: MCIMX27MJP4A
• Manufacturer: Freescale

Specifications of MCIMX27MJP4A

• Lead Free Status / RoHS Status: Compliant

4.3.9
Figure
ESDCTL module, which interfaces Mobile DDR or SDR SDRAM.
Table
Freescale Semiconductor
SD1
SD2
SD3
SD4
SD5
41, and
ID
37,
SDCLK
SDCLK
ADDR
DQM
RAS
CAS
Figure
WE
DQ
SDRAM (DDR and SDR) Memory Controller
CS
Table 42
CS, RAS, CAS, WE, DQM, CKE setup time
CS, RAS, CAS, WE, DQM, CKE hold time
SDRAM clock high-level width
SDRAM clock low-level width
SDRAM clock cycle time
SD4
SD6
SD4
38,
Figure
ROW/BA
list the timing parameters.
Table 37. DDR/SDR SDRAM Read Cycle Timing Parameters
39,
SD5
Figure 37. SDRAM Read Cycle Timing Diagram
SD5
SD7
Figure
SD10
Parameter
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
SD4
COL/BA
SD4
SD4
40,
SD5
SD5
Figure
SD5
41, and
SD8
Note: CKE is high during the read/write cycle.
Figure 42
Data
SD1
SD9
SD3
SD2
Table
Symbol
tCMS
tCMH
tCH
tCK
tCL
depict the timings pertaining to the
37,
Table
Min
3.4
3.4
7.5
2.0
1.8
38,
Electrical Characteristics
Table
Max
4.1
4.1
—
—
—
39,
Table
Unit
ns
ns
ns
ns
ns
40,
73