MCIMX27LMOP4A Freescale, MCIMX27LMOP4A Datasheet - Page 15

• Manufacturer Part Number: MCIMX27LMOP4A
• Manufacturer: Freescale

Specifications of MCIMX27LMOP4A

• Lead Free Status / RoHS Status: Compliant

2.3.12
The Enhanced Synchronous Dynamic RAM Controller (ESDRAMC) provides an interface and control for
synchronous DRAM memories for the system. SDRAM memories use a synchronous interface with all
signals registered on a clock edge. A command protocol is used for initialization, read, write, and refresh
operations to the SDRAM, and is generated on the signals by the controller (when required due to external
or internal requests). It has support for both single data rate RAMs and double data rate SDRAMs. It
supports 64 Mbits, 128 Mbits, 256 Mbits, and 512 Mbits, 1 Gbit, 2 Gbits, four bank synchronous DRAM
by two independent chip selects and with up to 256 Mbytes addressable memory per chip select.
2.3.13
The Fast Ethernet Controller (FEC) is designed to support both 10 and 100 Mbps
Ethernet/IEEE Std 802.3™ networks. An external transceiver interface and transceiver function are
required to complete the interface to the media. The FEC supports the 10/100 Mbps MII and the 10
Mbps-only 7-wire interface, which uses a subset of the MII pins for connection to an external Ethernet
transceiver.
The FEC incorporates the following features:
Freescale Semiconductor
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— Output format:
— Image Resize
Support for three different Ethernet physical interfaces:
— 100-Mbps IEEE 802.3 MII
— 10-Mbps IEEE 802.3 MII
— 10-Mbps 7-wire interface (industry standard)
IEEE 802.3 full duplex flow control
Programmable max frame length supports IEEE Std 802.1™ VLAN tags and priority
Support for full-duplex operation (200 Mbps throughput) with a minimum system clock rate of
50 MHz
Support for half-duplex operation (100 Mbps throughput) with a minimum system clock rate of
25 MHz
Retransmission from transmit FIFO following a collision (no processor bus utilization)
Automatic internal flushing of the receive FIFO for runts (collision fragments) and address
recognition rejects (no processor bus utilization)
Address recognition
— Frames with broadcast address may be always accepted or always rejected
– YUV 4:2:2 (YUYV)
– RGB16 and RGB32 bpp
– Upscaling ratios ranging from 1:1 to 1:4 in fractional steps
– Downscaling ratios ranging from 1:1 to 2:1 in fractional steps and a fixed 4:1
– Ratios provide scaling between QCIF, CIF, QVGA (320 × 240, 240 × 320)
Enhanced Synchronous Dynamic RAM Controller (ESDRAMC)
Fast Ethernet Controller (FEC)
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
Functional Description and Application Information
15