FDC37B787-NS Standard Microsystems (SMSC), FDC37B787-NS Datasheet - Page 143

• Manufacturer Part Number: FDC37B787-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B787-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

UF
The update-ended interrupt flag bit is set after
each update cycle.
"1", the "1" in UF causes the IRQF bit to be set
and asserts IRQB. A RESET_DRV or a read of
Register C causes UF to be cleared.
VRT
When a "1", this bit indicates that the contents of
the RTC are valid. A "0" appears in the VRT bit
when the battery voltage is low. The VRT bit is a
read-only bit, which can only be set by a read of
Register D. Refer to Power Management for the
conditions when this bit is reset. The processor
program can set the VRT bit when the time and
calendar are initialized to indicate that the time is
valid.
b6
Read as zero and cannot be written.
XTAL_
CAP
D7
MSB
VRT
b7
REGISTER D (DH) - BITS[7,6] ARE READ-ONLY, BITS[5:0] ARE READ/WRITE
D6
0
b6
0
When the UIE bit is also a
D5
0
b5
D4
0
b4
145
b3-0
The unused bits of Register C are read as zeros
and cannot be written.
b5:b0
Date Alarm; These bits store the date of month
alarm value. If set to 000000b, then a don’t care
state is assumed. The host must configure the
date alarm for these bits to do anything, yet they
can be written at any time. If the date alarm is
not enabled, these bits will return zeros. These
bits are not affected by RESET_DRV.
Note: Bits[6:0] are not accessible during an update
cycle.
REGISTER 7E (7Eh) CONTROL REGISTER 1
Default is 0; cleared upon Vbat POR. This
register is battery backed-up.
D3
0
b3
Date Alarm
VTR_POR
_EN
D2
b2
VTR_POR
_OFF
D1
b1
AL_REM_
LSB
EN
D0
b0