FDC37B787-NS Standard Microsystems (SMSC), FDC37B787-NS Datasheet - Page 193

• Manufacturer Part Number: FDC37B787-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B787-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Soft Power Status
Register 2
Default = 0x00
on Vbat POR
NAME
REG INDEX
0xB3 R/W
The following bits are the status for the wake-up
function of the nPowerOn bit. These indicate
which of the enabled wakeup functions caused the
power up.
1 = Occured
0 = Did not occur since last cleared
The following signals are latched to detect and hold
the soft power event (Type 1) (Note 1)
Bit[0] RXD1: UART 1 Receive Data; high to low
transition on the pin, cleared by a read of this
register
Bit[1] RXD2: UART 2 Receive Data; high to low
transition on the pin, cleared by a read of this
register
Bit[3] RING Status bit “RING_STS”; Latched, cleared
on read.
0= nRING input did not occur.
1= Ring indicator input occurred on the nRING pin
and, if enabled, caused the wakeup (activated
nPowerOn)
Bit[4] Reserved
Bit[5] CIR Status bit “CIR_STS”; latched, cleared
on read.
0= CIR wakeup event did not occur.
1= CIR wakeup event occurred and, if enabled,
caused the wakeup (activated nPowerOn).
The following signal is latched to detect and hold the
soft power event (Type 3) (Note 1) but the output of
the latch does not feed into the power down circuitry:
Bit[2] Button: Button pressed, Cleared by a read of
this register
Bits[7:6] Reserved
196
DEFINITION
STATE
C