AM53CF96KC/W AMD (ADVANCED MICRO DEVICES), AM53CF96KC/W Datasheet - Page 27

• Manufacturer Part Number: AM53CF96KC/W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM53CF96KC/W

• Lead Free Status / RoHS Status: Not Compliant

Synchronous Transfer Period Register (06H) Write
The Synchronous Transfer Period Register (STPREG)
contains a 5-bit value indicating the number of clock cy-
cles each byte will take to be transferred over the SCSI
bus in synchronous mode. The minimum value allowed
is 4. The STPREG defaults to 5 clocks/byte after a hard
or soft reset.
STPREG – Bits 7:5 – RES – Reserved
STPREG – Bits 4:0 – STP 4:0 – Synchronous
Transfer Period 4:0
The STP 4:0 bits are programmed to specify the syn-
chronous transfer period or the number of clock cycles
for each byte transfer in the synchronous mode. The
minimum value for STP 4:0 is 4 clocks/byte. Missing
table entries follow the binary code.
Synchronous Transfer Period Register
STPREG
RES
7
x
RES
6
x
RES
5
x
Am53CF94/Am53CF96
STP4
4
0
STP3
3
0
STP2
2
1
STP4
0
0
0
0
1
0
0
0
0
STP1
1
0
Address: 06
Type: Write
STP3
STP0
0
1
0
0
0
0
1
0
0
0
0
H
Synchronous Transfer Period 4:0
Reserved
Reserved
Reserved
STP2
1
1
1
1
1
0
0
0
0
17348B-25
STP1
0
0
1
1
1
0
0
1
1
STP0
0
1
0
1
1
0
1
0
1
AMD
Clocks/
Byte
31
32
33
34
35
4
5
6
7
27