MC33984BPNA Freescale, MC33984BPNA Datasheet - Page 23

• Manufacturer Part Number: MC33984BPNA
• Manufacturer: Freescale

Specifications of MC33984BPNA

• Switch Type: High Side
• Power Switch Family: MC33984B
• Power Switch On Resistance: 8mOhm
• Output Current: 30A
• Number Of Outputs: Dual
• Mounting: Surface Mount
• Supply Current: 20mA
• Package Type: Power QFN
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Pin Count: 16
• Lead Free Status / RoHS Status: Compliant

SPI PROTOCOL DESCRIPTION
synchronous data transfer with four I/O lines associated with
it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO),
and Chip Select (
most significant bit (MSB) first. All inputs are compatible with
5.0 V CMOS logic levels.
SERIAL CLOCK (SCLK)
33984 device. The serial input (SI) pin accepts data into the
input shift register on the falling edge of the SCLK signal
while the serial output (SO) pin shifts data information out of
the SO line driver on the rising edge of the SCLK signal. It is
important that the SCLK pin be in a logic low state whenever
CS
that the SCLK pin be in a Logic [0] state whenever the device
is not accessed (
internal pull-down, I
SCLK and SI pins are ignored and SO is tri-stated (high-
impedance). See
SERIAL INPUT (SI)
instruction is read on the falling edge of SCLK. An 8-bit
stream of serial data is required on the SI pin, starting with D7
D0) protocol with both input and output words transferring the
Analog Integrated Circuit Device Data
Freescale Semiconductor
The SPI interface has a full duplex, three-wire
The SI / SO pins of the 33984 follow a first-in first-out (D7/
The SPI lines perform the following functions:
Serial clocks (SCLK) the internal shift registers of the
This is a serial interface (SI) command data input pin. SI
makes any transition. For this reason, it is recommended
CS
CS
Figure 9
DWN
).
Logic [1] state). SCLK has an active
NOTES:
. When
and
Notes
1.
2.
3.
CS
Figure
CSB
SCLK
CS
SO
SO
SI
1.
2. D7:D0 relate to the most recent ordered entry of data into the device.
3. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
RSTB is in a logic 1 state during the above operation.
RST
D0, D1, D2, ..., and D7 relate to the most recent ordered entry of data into the SPSS
OD0, OD1, OD2, ..., and OD7 relate to the first 8 bits of ordered fault and status data out
of the device.
is Logic [1], signals at the
RST
10.
Figure 9. Single 8-Bit Word SPI Communication
is a Logic [1] state during the above operation.
D7
LOGIC COMMANDS AND REGISTERS
OD7
D6
OD6
D5
OD5
D4
OD4
D3
OD3
to D0. The internal registers of the 33984 are configured and
controlled using a 4-bit addressing scheme, as shown in
Table
in
I
SERIAL OUTPUT (SO)
register. The SO pin remains in a high-impedance state until
the
of reporting the status of the output, the device configuration,
and the state of the key inputs. The SO pin changes states on
the rising edge of SCLK and reads out on the falling edge of
SCLK. Fault and Input Status descriptions are provided in
Table
CHIP SELECT (CS)
microcontroller (MCU). When this pin is in a Logic [0] state,
the device is capable of transferring information to, and
receiving information from, the MCU. The 33984 device
latches in data from the Input shift registers to the addressed
registers on the rising edge of
information from the power output to the shift register on the
falling edge of
is Logic [0].
state only when SCLK is a Logic [0].
pull-up, I
DWN
Table
The SO data pin is a tri-stateable output from the shift
The
CS
.
D2
OD2
9. Register addressing and configuration are described
6.
pin is put into a Logic [0] state. The SO data is capable
CS
10. The SI input has an active internal pull-down,
UP
pin enables communication with the master
.
D1
CS
OD1
CS
should transition from a Logic [1] to a Logic [0]
D0
. The SO output driver is enabled when
OD0
LOGIC COMMANDS AND REGISTERS
FUNCTIONAL DEVICE OPERATION
CS
. The device transfers status
CS
has an active internal
33984
CS
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