PPC440GP-3FC400C Applied Micro Circuits Corporation, PPC440GP-3FC400C Datasheet - Page 13

• Manufacturer Part Number: PPC440GP-3FC400C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440GP-3FC400C

• Family Name: 440GP
• Device Core: PowerPC
• Device Core Size: 32/64Bit
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.9/1.95V
• Operating Supply Voltage (min): 1.65/1.7V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 552
• Package Type: FCBGA
• Lead Free Status / RoHS Status: Not Compliant

Revision 1.11 – August 27, 2010
IIC Bus Interface
Features include:
General Purpose Timers (GPT)
Provides a separate time base counter and additional system timers in addition to those defined in the processor
core.
General Purpose IO (GPIO) Controller
Universal Interrupt Controller (UIC)
Two Universal Interrupt Controllers (UIC) are available. They provide control, status, and communications
necessary between the external and internal sources of interrupts and the on-chip PowerPC processor.
Note: Processor specific interrupts (for example, page faults) do not use UIC resources.
Features include:
AppliedMicro Proprietary
Data Sheet
• Two IIC interfaces provided
• Support for Philips® Semiconductors I
• Operation at 100kHz or 400kHz
• 8-bit data
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Supports fixed V
• Two independent 4 x 1 byte data buffers
• Twelve memory-mapped, fully programmable configuration registers
• One programmable interrupt request signal
• Provides full management of all IIC bus protocols
• Programmable error recovery
• 32-bit Time Base Counter driven by the OPB bus clock
• Five 32-bit compare timers
• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master
• 31 of the 32 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO
• Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero,
• 13 external interrupts
• 45 internal interrupts
• Edge triggered or level-sensitive
• Positive or negative active
• Non-critical or critical interrupt to the on-chip processor core
• Programmable interrupt priority ordering
• Programmable critical interrupt vector for faster vector processing
accesses.
capabilities acts as a GPIO or is used for another purpose.
tri-stated if output bit is 1).
DD
IIC interface
2
C Specification, dated 1995
440GP – Power PC 440GP Embedded Processor
13