PPC440GX-3RF667C Applied Micro Circuits Corporation, PPC440GX-3RF667C Datasheet - Page 53

• Manufacturer Part Number: PPC440GX-3RF667C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440GX-3RF667C

• Family Name: 440GX
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.55/2.5V
• Operating Supply Voltage (max): 1.6/2.7V
• Operating Supply Voltage (min): 1.5/2.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 552
• Package Type: CBGA
• Lead Free Status / RoHS Status: Compliant

Revision 1.20 – June 9, 2009
Signal Functional Description
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ to GND)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to 3.3V) or pull-down (recommended value is 1kΩ to GND)
AMCC
PerData00:31
PerOE
PerPar0:3
PerReady
PerR/W
PerWE
External Master Peripheral Interface
BusReq
ExtAck
ExtReq
ExtReset
HoldAck
HoldReq
PerClk
PerErr
UART Peripheral Interface
UARTSerClk
UART0_Rx
UART0_Tx
UART0_DCD
UART0_DSR
UART0_CTS
Data Sheet
required
Signal Name
Peripheral data bus used by PPC440GX when not in external
master mode, otherwise used by external master.
Note: PerData00 is the most significant bit (msb) on this bus.
Used by either peripheral controller or DMA controller depending
upon the type of transfer involved. When the PPC440GX is the
bus master, it enables the selected device to drive the bus.
External peripheral data bus byte parity.
Used by a peripheral slave to indicate it is ready to transfer data.
Used by the PPC440GX when not in external master mode, as
output by either the peripheral controller or DMA controller
depending upon the type of transfer involved. High indicates a
read from memory, low indicates a write to memory.
Otherwise, it used by the external master as an input to indicate
the direction of transfer.
Write Enable. Low when any of the four PerWBE0:3 signals are
low.
Bus Request. Used when the PPC440GX needs to regain control
of peripheral interface from an external master.
External Acknowledgement. Used by the PPC440GX to indicate
that a data transfer occurred.
External Request. Used by an external master to indicate it is
prepared to transfer data.
Peripheral Reset. Used by an external master and by
synchronous peripheral slaves.
Hold Acknowledge. Used by the PPC440GX to transfer ownership
of peripheral bus to an external master.
Hold Request. Used by an external master to request ownership
of the peripheral bus.
Peripheral Clock. Used by an external master and by synchronous
peripheral slaves.
External Error. Used as an input to record external master errors
and external slave peripheral errors.
Serial clock input that provides an alternative to the internally
generated serial clock. Used in cases where the allowable
internally generated clock rates are not satisfactory. This input can
be individually connected to either or both UART0 and UART1.
UART0 Receive data.
UART0 Transmit data.
UART0 Data Carrier Detect.
UART0 Data Set Ready.
UART0 Clear To Send.
(Sheet 5 of 8)
Description
440GX – Power PC 440GX Embedded Processor
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Type
Notes
1, 2
1, 4
1, 5
1, 5
1, 4
1, 4
1, 4
1
2
1
2
4
6
6
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