IDT82V3001APV IDT, Integrated Device Technology Inc, IDT82V3001APV Datasheet - Page 4

• Manufacturer Part Number: IDT82V3001APV
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3001APV

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: SSOP
• Pin Count: 56
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

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Figure - 9
Figure - 10 Power-Up Reset Circuit.................................................................................................................................. 15
Figure - 11 IDT82V3001A Power Decoupling Scheme .................................................................................................... 16
Figure - 12 Input to Output Timing (Normal Mode)........................................................................................................... 25
Figure - 13 Output Timing 1.............................................................................................................................................. 26
Figure - 14 Output Timing 2.............................................................................................................................................. 27
Figure - 15 Input Control Setup and Hold Timing ............................................................................................................. 27
List of Figures
Block Diagram .................................................................................................................................................. 2
IDT82V3001A SSOP56 Package Pin Assignment........................................................................................... 6
State Control Block......................................................................................................................................... 10
State Control Diagram.................................................................................................................................... 11
TIE Control Circuit Diagram ........................................................................................................................... 12
State Switch with TIE Control Block Enabled................................................................................................. 13
State Switch with TIE Control Block Disabled ................................................................................................ 13
DPLL Block Diagram ...................................................................................................................................... 14
Clock Oscillator Circuit ................................................................................................................................... 15
LIST OF FIGURES
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October 15, 2008