CY7C09569V-83BBC Cypress Semiconductor Corp, CY7C09569V-83BBC Datasheet - Page 22

• Manufacturer Part Number: CY7C09569V-83BBC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09569V-83BBC

• Density: 576Kb
• Access Time (max): 18ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 45MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 14b
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 360mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 172
• Word Size: 36b
• Number Of Words: 16K
• Lead Free Status / RoHS Status: Not Compliant

Switching Waveforms
Counter Reset (Flow-Through Outputs)
Notes
Document Number: 38-06054 Rev. *D
64. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
65. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
66. CE = B0 = B1 = B2 = B3 = V
67. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
68. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATA
ADDRESS
INTERNAL
ADDRESS
DATA
CNTRST
during a valid WRITE cycle.
CNTEN
DATA
R/W
ADS
CLK
OUT
IN
A
t
SRST
X
t
HRST
t
CH2
IL
COUNTER
.
RESET
t
CYC2
(continued)
t
CL2
t
t
SD
SW
D
0
t
t
HD
HW
ADDRESS 0
WRITE
[64, 65, 66, 67, 68]
0
ADDRESS 0
t
CD1
READ
Q
0
ADDRESS 1
READ
t
SA
1
OUT
A
Q
n
1
should be in the High-Impedance state
t
HA
ADDRESS n
READ
A
A
n
n+1
CY7C09569V
CY7C09579V
Q
n
Page 22 of 32
A
n+1
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