LFX125EB-04F256I LATTICE SEMICONDUCTOR, LFX125EB-04F256I Datasheet - Page 19

• Manufacturer Part Number: LFX125EB-04F256I
• Description: FPGA ispXPGA® Family 139K Gates 1936 Cells EECMOS Technology 2.5V/3.3V 256-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFX125EB-04F256I

• Package: 256FBGA
• Family Name: ispXPGA®
• Device Logic Units: 1936
• Device System Gates: 139000
• Number Of Registers: 3800
• Typical Operating Supply Voltage: 2.5|3.3 V
• Maximum Number Of User I/os: 160
• Ram Bits: 94208
• Re-programmability Support: Yes

Lattice Semiconductor
Figure 17. ispXPGA PLL_RST and PLL_FBK Generation
Clock Routing
The Global Clock Lines (GCLK) have two sources, their dedicated pins and the sysCLOCK circuit. Figure 18 illus-
trates the generation of the Global Clock Lines.
Figure 18. Global Clock Line Generation
sysIO Capability
All the ispXPGA devices have eight sysIO banks, where each bank is capable of supporting multiple I/O standards.
Each sysIO bank has its own I/O supply voltage (V
bank complete independence from the others. Each I/O is individually configurable based on the bank’s V
V
latch. Table 4 lists the number of I/Os supported per bank in each of the ispXPGA devices. In addition, 5V tolerant
inputs are specified within an I/O bank that is connected to V
interfaces.
Table 5 lists the sysIO standards with the typical values for V
The TOE, JTAG TAP pins, PROGRAM, CFG0 and DONE pins of the ispXPGA device are the only pins that do not
have the sysIO capabilities. The TOE and CFG0 pins operate off the V
MOS standard corresponding to the device supply voltage. The TAP pins have a separate supply voltage (V
which determines the LVCMOS standard corresponding to that supply voltage.
There are three classes of I/O interface standards that are implemented in the ispXPGA devices. The first is the un-
terminated, single-ended interface. It includes the 3.3V LVTTL standard along with the 1.8V, 2.5V, and 3.3V LVC-
MOS interface standards. Additionally, PCI and AGP-1X are subsets of this type of interface.
GCLK0
GCLK1
GCLK2
GCLK3
REF
settings. In addition, each I/O has configurable drive strength, weak pull-up, weak pull-down, or a bus-keeper
PLL0
PLL1
PLL2
PLL3
CLK_OUT0
SEC_OUT0
CLK_OUT1
SEC_OUT1
CLK_OUT2
SEC_OUT2
CLK_OUT3
SEC_OUT3
I/O/PLL_RST
I/O/PLL_FBK
From Clock Net
From Routing
CLK0
CLK1
CLK2
CLK3
From Routing
From Routing
From Routing
From Routing
CCO
15
) and reference voltage (V
CLK7
CLK6
CLK5
CLK4
CCO,
CCO
of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI
V
REF
and V
CC
To PLL
To PLL
of the device, supporting only the LVC-
TT.
ispXPGA Family Data Sheet
SEC_OUT7
SEC_OUT6
SEC_OUT5
SEC_OUT4
CLK_OUT7
CLK_OUT6
CLK_OUT5
CLK_OUT4
REF
) resources allowing each
PLL7
PLL6
PLL5
PLL4
CCO
GCLK7
GCLK6
GCLK5
GCLK4
CCJ
and
),