LFXP3C-4T100I LATTICE SEMICONDUCTOR, LFXP3C-4T100I Datasheet - Page 96

• Manufacturer Part Number: LFXP3C-4T100I
• Description: FPGA LatticeXP Family 3000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 100-Pin TQFP Tray
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFXP3C-4T100I

• Package: 100TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 360 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 62
• Ram Bits: 55296
• Re-programmability Support: Yes

Lattice Semiconductor
LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.)
Number
AA20
AB21
AA21
AA22
W16
W17
W19
W18
W20
W21
W22
M20
M19
Ball
Y21
Y15
Y16
U19
U20
V19
V20
R19
R20
Y22
P19
P20
V21
U21
V22
U22
R21
N19
N20
R22
P22
P21
N21
N22
T20
T19
T21
T22
-
-
-
-
-
-
-
-
Function
GNDIO4
GNDIO4
GNDIO4
GNDIO3
GNDIO3
GNDIO3
GNDIO3
GNDIO3
GNDP1
PR35B
PR35A
PR34B
PR34A
PR33B
PR33A
PR32B
PR31A
PR30B
PR30A
PR29B
PR29A
PR28B
PR28A
PR26B
PR26A
PR25B
PR25A
PR24B
PR24A
PR23B
PR22A
PR21B
PR21A
PR20B
PR20A
PR19B
PR19A
PB36B
PB37A
PB37B
PB38A
PB38B
PB39A
Ball
-
-
-
-
-
-
Bank Diff.
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
-
-
-
-
-
-
LFXP10
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
C
T
C
T
C
T
C
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
Dual Function
VREF1_3
VREF2_3
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Function
GNDIO4
GNDIO4
GNDIO4
GNDIO3
GNDIO3
GNDIO3
GNDIO3
GNDIO3
GNDP1
PB41B
PB42A
PB42B
PB43A
PR39B
PR39A
PR38B
PR38A
PR37B
PR37A
PR36B
PR35A
PR34B
PR34A
PR33B
PR33A
PR32B
PR32A
PR30B
PR30A
PR29B
PR29A
PR28B
PR28A
PR27B
PR26A
PR25B
PR25A
PR24B
PR24A
PR23B
PR23A
PB43B
PB44A
PB44B
PB45A
PB46B
PB47A
PB47B
PB48A
Ball
Bank Diff.
4-37
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
LFXP15
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
C
T
C
T
C
T
C
T
C
C
T
C
T
C
T
C
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
Dual Function
VREF1_3
VREF2_3
DQS
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LatticeXP Family Data Sheet
Function
GNDIO4
GNDIO4
GNDIO4
GNDIO3
GNDIO3
GNDIO3
GNDIO3
GNDIO3
GNDP1
PB45B
PB46A
PB46B
PB47A
PB47B
PB48A
PB48B
PB49A
PB50B
PB51A
PB51B
PB52A
PR43B
PR43A
PR42B
PR42A
PR41B
PR41A
PR40B
PR39A
PR38B
PR38A
PR37B
PR37A
PR36B
PR36A
PR34B
PR34A
PR33B
PR33A
PR32B
PR32A
PR31B
PR30A
PR29B
PR29A
PR28B
PR28A
PR27B
PR27A
Ball
Bank Diff.
Pinout Information
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
LFXP20
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
Dual Function
VREF1_3
VREF2_3
DQS
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-