MC145483DW Freescale, MC145483DW Datasheet - Page 4

• Manufacturer Part Number: MC145483DW
• Manufacturer: Freescale
• Type: PCMr

Specifications of MC145483DW

• Number Of Channels: 1
• Gain Control: Adjustable
• Number Of Adc's: 1
• Number Of Dac's: 1
• Adc/dac Resolution: 13b
• Package Type: SOIC W
• Sample Rate: 8KSPS
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Operating Supply Voltage (min): 2.7V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 20
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

POWER SUPPLY
V DD
Positive Power Supply (Pin 6)
nected to + 3 V. This pin should be decoupled to V SS with a
0.1 µF ceramic capacitor.
V SS
Negative Power Supply (Pin 15)
connected to 0 V.
V AG
Analog Ground Output (Pin 20)
pin should be decoupled to V SS with a 0.01 µF ceramic ca-
pacitor. All analog signal processing within this device is ref-
erenced to this pin. If the audio signals to be processed are
referenced to V SS , then special precautions must be utilized
to avoid noise between V SS and the V AG pin. Refer to the ap-
plications information in this document for more information.
The V AG pin becomes high impedance when this device is in
the powered–down mode.
V AG Ref
Analog Ground Reference Bypass (Pin 1)
ry that generates the mid–supply voltage for the V AG output
pin. This pin should be bypassed to V SS with a 0.1 µF ceram-
ic capacitor using short, low inductance traces. The V AG Ref
pin is only used for generating the reference voltage for the
V AG pin. Nothing is to be connected to this pin in addition to
the bypass capacitor. All analog signal processing within this
device is referenced to the V AG pin. If the audio signals to be
processed are referenced to V SS , then special precautions
must be utilized to avoid noise between V SS and the V AG pin.
Refer to the applications information in this document for
more information. When this device is in the powered–down
mode, the V AG Ref pin is pulled to the V DD power supply with
a non–linear, high–impedance circuit.
CONTROL
HB
Transmit High–Pass Filter Bypass (Pin 16)
be used or bypassed, which allows frequencies below
200 Hz to appear at the input of the ADC to be digitized. This
high–pass filter is a third order filter for attenuating power line
frequencies, typically 50/60 Hz. A logic low selects this filter.
A logic high deselects or bypasses this filter. When the filter
is bypassed, the transmit frequency response extends down
to dc.
PDI
Power–Down Input (Pin 10)
when a logic 0 is applied. When this device is powered down,
all of the clocks are gated off and all bias currents are turned
off, which causes RO–, PO–, PO+, TG, V AG , and DT to be-
come high impedance. The device will operate normally
This is the most positive power supply and is typically con-
This is the most negative power supply and is typically
This output pin provides a mid–supply analog ground. This
This pin is used to capacitively bypass the on–chip circuit-
This pin selects whether the transmit high–pass filter will
This pin puts the device into a low power dissipation mode
PIN DESCRIPTIONS
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when a logic 1 is applied to this pin. The device goes through
a power–up sequence when this pin is taken to a logic 1
state, which prevents the DT PCM output from going low im-
pedance for at least two FST cycles. The V AG and V AG Ref
circuits and the signal processing filters must settle out be-
fore the DT PCM output or the RO– receive analog output
will represent a valid analog signal.
ANALOG INTERFACE
TI+
Transmit Analog Input (Non–Inverting) (Pin 19)
setting operational amplifier. This pin accommodates a differ-
ential to single–ended circuit for the input gain setting op
amp. This allows input signals that are referenced to the V SS
pin to be level shifted to the V AG pin with minimum noise.
This pin may be connected to the V AG pin for an inverting
amplifier configuration if the input signal is already refer-
enced to the V AG pin. The common mode range of the TI+
and TI– pins is from 1.2 V, to V DD minus 1.2 V. This is an FET
gate input.
transmit input multiplexer. Connecting the TI+ pin to V DD will
place this amplifier’s output (TG) into a high–impedance
state, and selects the TG pin to serve as a high–impedance
input to the transmit filter. Connecting the TI+ pin to V SS will
also place this amplifier’s output (TG) into a high–impedance
state, and selects the TI– pin to serve as a high–impedance
input to the transmit filter.
TI–
Transmit Analog Input (Inverting) (Pin 18)
erational amplifier. Gain setting resistors are usually con-
nected from this pin to TG and from this pin to the analog
signal source. The common mode range of the TI+ and TI–
pins is from 1.2 V to V DD – 1.2 V. This is an FET gate input.
plexer pins when the TI+ pin is connected to V SS . When TI+
is connected to V DD , this pin is ignored. See the pin descrip-
tions for the TI+ and the TG pins for more information.
TG
Transmit Gain (Pin 17)
amplifier and the input to the transmit band–pass filter. This
op amp is capable of driving a 2 kΩ load. Connecting the TI+
pin to V DD will place the TG pin into a high–impedance state,
and selects the TG pin to serve as a high–impedance input to
the transmit filter. All signals at this pin are referenced to the
V AG pin. When TI+ is connected to V SS , this pin is ignored.
See the pin descriptions for TI+ and TI– pins for more in-
formation. This pin is high impedance when the device is in
the powered–down mode.
RO–
Receive Analog Output (Inverting) (Pin 2)
from the digital–to–analog converter. This output is capable
of driving a 2 kΩ load to 0.886 V peak referenced to the V AG
pin. If the device is operated half–channel with the FST pin
clocking and FSR pin held low, the receive filter input will be
This is the non–inverting input of the transmit input gain
The TI+ pin also serves as a digital input control for the
This is the inverting input of the transmit gain setting op-
The TI– pin also serves as one of the transmit input mulit-
This is the output of the transmit gain setting operational
This is the inverting output of the receive smoothing filter