AD9434BCPZ-370 Analog Devices Inc, AD9434BCPZ-370 Datasheet
AD9434BCPZ-370
Specifications of AD9434BCPZ-370
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AD9434BCPZ-370 Summary of contents
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FEATURES SNR = 65 dBFS 250 MHz at 500 MSPS IN ENOB of 10.5 bits 250 MHz at 500 MSPS (−1.0 dBFS) IN SFDR = 78 dBc 250 ...
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AD9434 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications .......................................................................... 4 Digital Specifications ...
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SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN Table 1. 1 Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) INTERNAL REFERENCE VREF TEMPERATURE DRIFT ...
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AD9434 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN Table Parameter SNR f = 30.3 MHz 70.3 MHz 100.3 MHz ...
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DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN Table 3. 1 Parameter CLOCK INPUTS Logic Compliance Internal Common-Mode Bias Differential Input Voltage High Level Input ( Low Level Input (V ) ...
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AD9434 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN Table 4. Parameter Maximum Conversion Rate Minimum Conversion Rate 1, 2 CLK+ Pulse Width High ( CLK+ Pulse Width Low (t ) ...
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Timing Diagrams N – 1 VIN+, VIN– CLK+ CLK– t CPD DCO+ DCO– Dx+ Dx– N – 1 VIN+, VIN– CLK+ CLK– t CPD DCO+ DCO– D0/D6+ D0/D6– D5/D11+ D5/D11– ...
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AD9434 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Electrical AVDD to AGND −0 +2.0 V DRVDD to DRGND −0 +2.0 V AGND to DRGND −0 +0.3 V AVDD to DRVDD −2 +2.0 ...
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 7. Pin Function Descriptions—Single Data Rate Mode Pin No. Mnemonic 1 0 AGND 30 34 39, AVDD 24, 47 DRVDD 1 8, 23, 48 DRGND ...
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AD9434 Pin No. Mnemonic 4 D4+ 5 D5− 6 D5+ 9 D6− 10 D6+ 11 D7− 12 D7+ 13 D8− 14 D8+ 15 D9− 16 D9+ 17 D10− 18 D10+ 19 D11− 20 D11+ 21 OR− 22 OR+ 1 AGND ...
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Table 8. Pin Function Descriptions—Double Data Rate Mode Pin No. Mnemonic 1 0 AGND 30 34 39, 41 AVDD to 43 24, 47 DRVDD 1 8, 23, 48 DRGND 35 VIN+ 36 VIN− 40 ...
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AD9434 Pin No. Mnemonic 6 D5/D11+ 9 OR− 20, 28 DNC 21 DNC/(OR−) 22 DNC/(OR+) 1 Tie AGND and DRGND to a common quiet ground plane. Description D5/D11 True Output (MSB). Overrange Complement Output. (This pin ...
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TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate 370MSPS 30.3MHz AT –1.0dBFS –20 SNR: 65.4dB ENOB: 10.7 BITS SFDR: 90dBc –40 –60 –80 –100 –120 100 FREQUENCY ...
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AD9434 0 491.52MSPS 368.3MHz AT –1.0dBFS –20 SNR: 64.0dB ENOB: 10.5 BITS SFDR: 79dBc –40 –60 –80 –100 –120 100 120 140 160 180 FREQUENCY (MHz) Figure 12. AD9434-500 64k Point Single-Tone; 491.52 MSPS, 368.3 ...
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SFDR (dBFS) 80 SNR (dBFS SFDR (dBc SNR (dB –90 –80 –70 –60 –50 –40 AMPLITUDE (dB) Figure 18. AD9434-370 SNR/SFDR vs. Input Amplitude; 500 MSPS, 140.3 MHz 100 90 ...
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AD9434 2.5 2.0 1.5 1.0 0 – – – BINS Figure 24. AD9434-370 Grounded Input Histogram; 370 MSPS 2.5 2.0 1.5 1.0 0 – – ...
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SFDR (dBc AD9434, 370MSPS 70 65 SNR (dBFS) AD9434, 500MSPS 1.5 1.6 1.7 1.8 V (V) CM Figure 30. SNR/SFDR vs. Common-Mode Voltage; 370 MSPS, 500 MSPS 140.3 MHz IN 350 ...
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AD9434 EQUIVALENT CIRCUITS AVDD AVDD 0.9V 15kΩ 15kΩ CLK+ Figure 33. Clock Inputs AVDD CML AVDD VIN+ 500Ω AVDD 500Ω SPI CONTROLLED VIN+ Figure 34. Analog Input DC Equivalent Circuit (V DRVDD 350Ω SCLK/DFS 30kΩ Figure 35. Equivalent SCLK/DFS, PDWN ...
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THEORY OF OPERATION The AD9434 architecture consists of a front-end sample-and- hold amplifier (SHA) followed by a pipelined switched capacitor ADC. The quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. The ...
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AD9434 ANALOG INPUT ANALOG INPUT CLOCK INPUT CONSIDERATIONS For optimum performance, drive the AD9434 sample clock inputs (CLK+ and CLK−) with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. ...
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Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals result, these ADCs may be sensitive to clock duty cycle tolerance is commonly required on the ...
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AD9434 14 500 12 400 300 10 200 100 –100 –200 4 –300 –400 2 –500 0 –3 –2 – –40 TIME (ns) Figure 49. Data Eye for LVDS Outputs in ANSI Mode ...
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There are three pins that define the serial port interface (SPI) to this particular ADC. They are the SCLK/DFS, SDIO, and CSB pins. The SCLK/DFS (serial clock) is used to synchronize the read and write data presented to the ADC. ...
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AD9434 CSB SCLK DON’T CARE W1 W0 SDIO DON’T CARE R/W Table 11. Serial Timing Definitions Parameter Min (ns CLK ...
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MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table (see Table 13) has eight address locations. The memory map is roughly divided into three sections: chip configuration register map (Address 0x00 to Address 0x02), transfer ...
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AD9434 Addr. Bit 7 (Hex) Register Name (MSB) 10 Offset 0D TEST_IO (For user-defined mode only, set Bits[3:0] = 1000 Pattern 1 only 01 = toggle P1/ toggle P1/0000 11 = toggle P1/P2/ 0000 0F AIN_CONFIG ...
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Addr. Bit 7 (Hex) Register Name (MSB) 18 FLEX_VREF VREF select 00 = internal V (20 kΩ pull-down import V (0. 0 VREF pin export V (from internal reference not ...
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... Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] LVDS Evaluation Board with AD9434BCPZ-370 LVDS Evaluation Board with AD9434BCPZ-500 D09383-0-5/11(A) Rev Page ...