LFXP2-40E-5FN672I Lattice, LFXP2-40E-5FN672I Datasheet - Page 17

• Manufacturer Part Number: LFXP2-40E-5FN672I
• Description: IC DSP 40KLUTS 540I/O 672FPBGA
• Manufacturer: Lattice

Specifications of LFXP2-40E-5FN672I

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 906240
• Number Of I /o: 540
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1131

Lattice Semiconductor
Figure 2-12. Secondary Clock Selection
Slice Clock Selection
Figure 2-13 shows the clock selections and Figure 2-14 shows the control selections for Slice0 through Slice2. All
the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals, via routing,
can be used as clock inputs to the slices. Slice controls are generated from the secondary clocks or other signals
connected via routing.
If none of the signals are selected for both clock and control, then the default value of the mux output is 1. Slice 3
does not have any registers; therefore it does not have the clock or control muxes.
Figure 2-13. Slice0 through Slice2 Clock Selection
4 Secondary Clocks/CE/LSR (SC0 to SC3) per Region
SC0
24:1
Secondary Clock
Primary Clock
SC1
24:1
Clock/Control
Routing
Secondary Clock Feedlines: 8 PIOs + 16 Routing
SC2
Vcc
24:1
SC3
12
24:1
8
4
1
4 High Fan-out Data Signals (SC4 to SC7) per Region
2-14
SC4
24:1
25:1
SC5
High Fan-out Data
24:1
Clock to Slice
SC6
LatticeXP2 Family Data Sheet
24:1
SC7
24:1
Architecture