LCMXO2-1200ZE-1MG132CR1 Lattice, LCMXO2-1200ZE-1MG132CR1 Datasheet - Page 78

• Manufacturer Part Number: LCMXO2-1200ZE-1MG132CR1
• Description: IC PLD 1280LUTS 105I/O 132CSBGA
• Manufacturer: Lattice

Specifications of LCMXO2-1200ZE-1MG132CR1

• Programmable Type: *
• Number Of Macrocells: *
• Voltage - Input: *
• Speed: *
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1140

April 2011
Signal Descriptions
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or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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General Purpose
P[Edge] [Row/Column
Number]_[A/B/C/D]
NC
GND
VCC
VCCIOx
PLL and Clock Functions (Used as user-programmable I/O pins when not used for PLL or clock pins)
[LOC]_GPLL[T, C]_IN
[LOC]_GPLL[T, C]_FB
PCLK [n]_[2:0]
Test and Programming (Dual function pins used for test access port and during sysCONFIG™)
TMS
TCK
TDI
TDO
JTAGENB
Configuration (Dual function pins used during sysCONFIG)
PROGRAMN
INITN
DONE
Signal Name
I/O
I/O
I/O
I/O
—
—
—
—
—
—
—
O
I
I
I
I
I
[Edge] indicates the edge of the device on which the pad is located. Valid edge designations
are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on which the PIO
Group exists. When Edge is T (Top) or (Bottom), only need to specify Row Number. When
Edge is L (Left) or R (Right), only need to specify Column Number.
[A/B/C/D] indicates the PIO within the group to which the pad is connected.
Some of these user-programmable pins are shared with special function pins. When not used
as special function pins, these pins can be programmed as I/Os for user logic.
During configuration of the user-programmable I/Os, the user has an option to tri-state the 
I/Os and enable an internal pull-up, pull-down or buskeeper resistor. This option also applies
to unused pins (or those not bonded to a package pin). The default during configuration is for
user-programmable I/Os to be tri-stated with an internal pull-down resistor enabled. When the
device is erased, I/Os will be tri-stated with an internal pull-down resistor enabled. Some pins,
such as PROGRAMN and JTAG pins, default to tri-stated I/Os with pull-up resistors enabled
when the device is erased.
No connect.
GND – Ground. Dedicated pins.
V
VCCIO – The power supply pins for I/O Bank x. Dedicated pins.
Reference Clock (PLL) input pads: [LOC] indicates location. Valid designations are L (Left
PLL) and R (Right PLL). T = true and C = complement.
Optional Feedback (PLL) input pads: [LOC] indicates location. Valid designations are L (Left
PLL) and R (Right PLL). T = true and C = complement.
Primary Clock pads. One to three clock pads per side.
Test Mode Select input pin, used to control the 1149.1 state machine.
Test Clock input pin, used to clock the 1149.1 state machine.
Test Data input pin, used to load data into the device using an 1149.1 state machine.
Output pin – Test Data output pin used to shift data out of the device using 1149.1.
Optionally controls behavior of TDI, TDO, TMS, TCK. If the device is configured to use the
JTAG pins (TDI, TDO, TMS, TCK) as general purpose I/O, then:
If JTAGENB is low: TDI, TDO, TMS and TCK can function a general purpose I/O.
If JTAGENB is high: TDI, TDO, TMS and TCK function as JTAG pins.
For more details, refer to TN1204,
Initiates configuration sequence when asserted low. This pin always has an active pull-up.
Open Drain pin. Indicates the FPGA is ready to be configured. During configuration, a pull-up
is enabled.
Open Drain pin. Indicates that the configuration sequence is complete, and the start-up
sequence is in progress.
CC
– The power supply pins for core logic. Dedicated pins.
MachXO2 Family Data Sheet
4-1
MachXO2 Programming and Configuration Usage
Descriptions
Pinout Information
DS1035
Preliminary Data Sheet DS1035
Pinout Information_01.2
Guide.