IDTCV132BPVG8 IDT, Integrated Device Technology Inc, IDTCV132BPVG8 Datasheet - Page 7

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IDTCV132BPVG8

Manufacturer Part Number
IDTCV132BPVG8
Description
IC FLEXPC CLK PROGR P4 56-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
FlexPC™r
Type
PC Clockr
Datasheet

Specifications of IDTCV132BPVG8

Input
Crystal
Output
Clock
Frequency - Max
200MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-SSOP
Frequency-max
200MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
CV132BPVG8
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
NOTES:
1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
2. This parameter is guaranteed by design, but not 100% production tested.
3. See TIMING DIAGRAMS for timing requirements.
IDTCV132B
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
Symbol
I
I
DD3.3OP
DD3.3PD
T
C
C
L
C
V
V
I
I
STAB
I
IL1
IL2
F
OUT
PIN
IH
INX
IH
IL
IN
I
3.3V Input HIGH Voltage
3.3V Input LOW Voltage
Input HIGH Current
Input LOW Current
Input LOW Current
Operating Supply Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
Clock Stabilization
Modulation Frequency
T
T
T
T
T
T
T
DRIVE
FALL
RISE
DRIVE
DRIVE
FALL
RISE
_PD#
_PD#
_CPU_Stop#
_CPU_Stop#
_SRC
_PD#
_CPU_Stop#
A
= 0°C to +70°C, Supply Voltage: V
(2)
(2)
Parameter
(2)
(2)
(2)
(1)
(2)
(2,3)
(2)
(2)
(2)
(2)
3.3V ± 5%
3.3V ± 5%
V
V
V
Full active, C
All differential pairs driven
All differential pairs tri-stated
V
Logic inputs
Output pin capacitance
X1 and X2 pins
From V
Triangular modulation
SRC output enable after PCI_Stop# de-assertion
CPU output enable after PD# de-assertion
Fall time of PD#
Rise time of PD#
CPU output enable after CPU_Stop# de-assertion
Fall time of PD#
Rise time of PD#
IN
IN
IN
DD
= V
= 0V, inputs with no pull-up resistors
= 0V, inputs with pull-up resistors
= 3.3V
DD
DD
DD
power-up or de-assertion of PD# to first clock
= 3.3V ± 5%
L
= full load
Test Conditions
7
COMMERCIAL TEMPERATURE RANGE
V
SS
Min.
–200
–5
–5
30
2
- 0.3
14.31818
Typ.
V
DD
Max.
400
300
0.8
1.8
70
12
33
15
10
5
7
5
6
5
5
5
5
5
+ 0.3
MHz
Unit
KHz
µA
µA
µA
mA
mA
nH
ms
pF
ns
us
ns
ns
us
ns
ns
V
V

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