ICS95V157AG IDT, Integrated Device Technology Inc, ICS95V157AG Datasheet

IC CLK DVR SSTL_2 2.5V 48-TSSOP

ICS95V157AG

Manufacturer Part Number
ICS95V157AG
Description
IC CLK DVR SSTL_2 2.5V 48-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of ICS95V157AG

Input
Clock
Output
SSTL-2
Frequency - Max
233MHz
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Frequency-max
233MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
95V157AG
2.5V Single-Ended to SSTL_2 Clock Driver (45MHz - 233MHz)
Recommended Application:
Single-ended clock input with zero delay board fan out
Product Description/Features:
Switching Characteristics:
Block Diagram
0501C—11/24/08
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL_2)
Feedback pin for input to output synchronization
PD# for power management
Spread Spectrum tolerant inputs
CYCLE - CYCLE jitter: <60ps
OUTPUT - OUTPUT skew: <60ps
Period jitter: ±30ps
DUTY CYCLE: 49.5% - 50.5%
Integrated
Circuit
Systems, Inc.
Functionality
A
n (
n (
n (
n (
G
G
2
2
2
2
V
5 .
5 .
5 .
5 .
N
N
o
o
o
o
D
m
m
m
m
V
V
V
V
D
D
D
)
)
)
)
N I
P
6.10 mm. Body, 0.50 mm. pitch = TSSOP
D
H
H
L
L
H
H
P
#
U
T
S
C
L
Pin Configuration
K
H
H
H
L
L
L
_
N I
T
48-Pin TSSOP
C
L
H
Z
Z
H
L
L
K
T
C
O
L
U
H
L
Z
Z
H
L
K
T
C
P
U
F
T
ICS95V157
B
S
_
O
H
Z
Z
H
L
L
U
T
T
B
B
P
y
y
p
p
L
a
a
L
s s
s s
o
o
o
o
S
f f
f f
n
n
e
e
a t
d
d
e t
o /
o /
f f
f f

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ICS95V157AG Summary of contents

Page 1

Integrated Circuit Systems, Inc. 2.5V Single-Ended to SSTL_2 Clock Driver (45MHz - 233MHz) Recommended Application: Single-ended clock input with zero delay board fan out Product Description/Features: • Low skew, low jitter PLL clock driver • differential clock ...

Page 2

ICS95V157 Pin Descriptions ...

Page 3

Absolute Maximum Ratings Supply Voltage (VDD & AVDD -0.5V to 4.6V Logic Inputs . . . . . . . . . . . . . . . . ...

Page 4

ICS95V157 Recommended Operating Condition (see note1 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) A PARAMETER SYMBOL Supply Voltage Low level input voltage V IL High level ...

Page 5

Timing Requirements 85°C; Supply Voltage A A VDD PARAMETER SYMBOL Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization Switching Characteristics (see note 3) PARAMETER Low-to high level propagation delay time High-to low ...

Page 6

ICS95V157 Y , FB_OUTC FB_OUTT X 0501C—11/24/08 6 ...

Page 7

CLK_INC CLK_INT FB_INC FB_INT FB_OUTC FB_OUTT FB_OUTC FB_OUTT FB_OUTC FB_OUTT X 0501C—11/24/08 Parameter Measurement Information ...

Page 8

ICS95V157 Y , FB_OUTC FB_OUTT X 20% Clock Inputs and Outputs 0501C—11/24/08 Parameter Measurement Information t (hper_n) t (hper_n+ (jit_Hper) (jit_Hper_n) 2xf O Figure 7. Half-Period Jitter 80% Rise ...

Page 9

INDEX INDEX AREA AREA aaa 6.10 mm. Body, 0.50 mm. pitch TSSOP (20 mil) (240 mil) Ordering Information 95V157yG - T Example: XXXX ...

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