ICS93V855AGLFT IDT, Integrated Device Technology Inc, ICS93V855AGLFT Datasheet
ICS93V855AGLFT
Specifications of ICS93V855AGLFT
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ICS93V855AGLFT Summary of contents
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Integrated Circuit Systems, Inc. DDR Phase Lock Loop Clock Driver Recommended Application: DDR Clock Driver Product Description/Features: • Low skew, low jitter PLL clock driver • External feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • ...
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ICS93V855 Pin Descriptions PIN # PIN NAME PIN TYPE 1 GND PWR 2 DDRC0 OUT 3 DDRT0 OUT 4 VDD2.5 PWR 5 CLK_INT IN 6 CLK_INC IN 7 AVDD2.5 PWR 8 AGND PWR 9 GND PWR 10 DDRC1 OUT 11 ...
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Absolute Maximum Ratings Supply Voltage: (VDD & AVDD -0.5V to 3.6V (VDDI -0.5V to 4.6V Logic ...
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ICS93V855 DC Electrical Characteristics TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) SYMBOL PARAMETER V Supply Voltage DDQ V Low level input voltage V High level input voltage DC input signal ...
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Switching Characteristics T = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) A PARAMETER 3 Max clock frequency Application Frequency 3 Range Input clock duty cycle Input clock slew rate CLK stabilization Low-to ...
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ICS93V855 V DD/2 ICS93V855 -V DD/2 NOTE: V (TT) = GND Y , FB_OUTC FB_OUTT X 0497B—06/01/04 Parameter Measurement Information (CLKC) V (CLKC) ICS93V855 GND Figure 1. IBIS Model Output Load ...
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CLK_INC CLK_INT FB_INC FB_INT FB_OUTC FB_OUTT FB_OUTC FB_OUTT FB_OUTC FB_OUTT X 0497B—06/01/04 Parameter Measurement Information ...
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ICS93V855 Y , FB_OUTC FB_OUTT X 20% Clock Inputs and Outputs 0497B—06/01/04 Parameter Measurement Information t jit(hper_n+1) t jit(hper_n jit(hper) jit(hper_n) 2xf O Figure 7. Half-Period Jitter 80% t ...
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INDEX INDEX AREA AREA SEATING SEATING b PLANE PLANE aaa 4.40 mm. Body, 0.65 mm. pitch TSSOP (0.0256 Inch) (173 mil) Ordering Information ICS93V855yGT Example: ICS XXXXXX y ...